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[209.132.180.67]) by mx.google.com with ESMTP id q14-v6si1760520pli.419.2018.05.31.13.31.00; Thu, 31 May 2018 13:31:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754369AbeEaUae (ORCPT + 99 others); Thu, 31 May 2018 16:30:34 -0400 Received: from mail.bootlin.com ([62.4.15.54]:33644 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753983AbeEaUac (ORCPT ); Thu, 31 May 2018 16:30:32 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 609F02073C; Thu, 31 May 2018 22:30:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from bbrezillon (unknown [91.160.177.164]) by mail.bootlin.com (Postfix) with ESMTPSA id B9E292071D; Thu, 31 May 2018 22:30:29 +0200 (CEST) Date: Thu, 31 May 2018 22:30:27 +0200 From: Boris Brezillon To: Stefan Agner Cc: Miquel Raynal , robh+dt@kernel.org, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, mark.rutland@arm.com, thierry.reding@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, dev@lynxeye.de, richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, benjamin.lindqvist@endian.se, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mirza.krak@gmail.com, linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Message-ID: <20180531223027.57e36d0b@bbrezillon> In-Reply-To: <047a9a5e72c8db52858a505865d4f720@agner.ch> References: <86fdf19ec92b732709732fb60199f16488b4b727.1526990589.git.stefan@agner.ch> <20180528000422.7f18dc5f@xps13> <047a9a5e72c8db52858a505865d4f720@agner.ch> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 31 May 2018 19:54:08 +0200 Stefan Agner wrote: > >> + > >> + mtd->dev.parent = &pdev->dev; > >> + mtd->name = "tegra_nand"; > > > > I just figured it was undocumented (yet) but you could have a label > > string property in your nand DT node that tells you the name of the > > MTD device instead of something too generic like tegra_nand. > > > > Using label in the NAND chip subnode actually causes current U-Boot to > delete (!!) the chip node and create partitions on the controller node. > > See: > https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757 > > The code essentially uses the property label to detect whether its a > NAND chip or a partition... Why not fixing that in uboot? The representation where the NAND device and NAND controller are mixed in a single node called nand@xxx is just wrong from a HW PoV, and it seems uboot is using this representation, which is probably why you have a problem when trying to find the partition directly under the NAND controller node. > > At least this is the case when using fdt_fixup_mtdparts and passing the > controller compatible ("nvidia,tegra20-nand") in node_info, Just a digression, but I recommend using "nvidia,tegra20-nand-controller" for the compatible, because the node is describing the NAND controller not the NAND chip. > what our > downstream U-Boot is currently doing. Maybe we should pass the > compatible property of the NAND chip? Or maybe you should search for partitions in children of the controller node instead of searching directly under the controller node itself. > But afaik, chips do not have a > compatible necessarily. Nope, and it should stay like that. > > So using label in the chip node is currently a no-go for me. I hope I'm wrong but I fear this is not the only problem you'll face when switching to a controller+chip representation. This is just the tip of the iceberg. > > Will send out v3 soon. Sure, let's see how v3 looks.