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[209.132.180.67]) by mx.google.com with ESMTP id b1-v6si39911023pla.570.2018.05.31.23.48.30; Thu, 31 May 2018 23:48:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DkuGUoR5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750981AbeFAGsD (ORCPT + 99 others); Fri, 1 Jun 2018 02:48:03 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:51587 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbeFAGsB (ORCPT ); Fri, 1 Jun 2018 02:48:01 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w516l7bg011712; Fri, 1 Jun 2018 01:47:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1527835627; bh=yprdy+/KwIAtA6vg4yV0WiO8mKJJT2AkvOmovbPzaks=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=DkuGUoR5Hx1rSqzRUzdKUtaYw+7z4KaRrgRHsTJQQw8brWicruUASsR+4P2Ejk339 y+eplqEzOlxxG0kQ7vodGiZ7MKnI4ik11E3BirMVt7KDzROlbtHLw8+ToiO135qaCs 4BDcUIHJhN2vfEeLCouihOD+WoG25XhB1byML1Yo= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w516l7J8029611; Fri, 1 Jun 2018 01:47:07 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 1 Jun 2018 01:47:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 1 Jun 2018 01:47:07 -0500 Received: from [172.24.190.215] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w516l3RC010054; Fri, 1 Jun 2018 01:47:04 -0500 Subject: Re: [PATCH v2 3/6] clk: ti: dra7: Add clkctrl clock data for the mcan clocks To: Tero Kristo , Rob Herring CC: , , , , , , , References: <20180530141133.3711-1-faiz_abbas@ti.com> <20180530141133.3711-4-faiz_abbas@ti.com> <20180531040350.GA25132@rob-hp-laptop> <678ef467-a235-91db-8bae-f249ad98eac8@ti.com> From: Faiz Abbas Message-ID: Date: Fri, 1 Jun 2018 12:18:37 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <678ef467-a235-91db-8bae-f249ad98eac8@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thursday 31 May 2018 06:59 PM, Tero Kristo wrote: > On 31/05/18 13:14, Faiz Abbas wrote: >> Hi, >> >> On Thursday 31 May 2018 09:33 AM, Rob Herring wrote: >>> On Wed, May 30, 2018 at 07:41:30PM +0530, Faiz Abbas wrote: >>>> Add clkctrl data for the m_can clocks and register it within the >> ... >>>>   diff --git a/include/dt-bindings/clock/dra7.h >>>> b/include/dt-bindings/clock/dra7.h >>>> index 5e1061b15aed..d7549c57cac3 100644 >>>> --- a/include/dt-bindings/clock/dra7.h >>>> +++ b/include/dt-bindings/clock/dra7.h >>>> @@ -168,5 +168,6 @@ >>>>   #define DRA7_COUNTER_32K_CLKCTRL    DRA7_CLKCTRL_INDEX(0x50) >>>>   #define DRA7_UART10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x80) >>>>   #define DRA7_DCAN1_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88) >>>> +#define DRA7_ADC_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0) >>> >>> ADC and mcan are the same thing? >>> >> >> The register to control MCAN clocks is called ADC_CLKCTRL, Yes. > > Is there any reason for this or is that just a documentation bug? > Looks like they meant to have an ADC in dra74 or dra72 but decided against it and then many years later used the same registers for MCAN instead. You can see ADC_CLKCTRL exists in dra72 TRM but is explicitly disabled. http://www.ti.com/lit/ug/spruic2b/spruic2b.pdf pg:1524 Thanks, Faiz