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[209.132.180.67]) by mx.google.com with ESMTP id k22-v6si7665987pll.416.2018.06.02.07.08.41; Sat, 02 Jun 2018 07:08:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=izhakypA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751417AbeFBOHn (ORCPT + 99 others); Sat, 2 Jun 2018 10:07:43 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:45346 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750740AbeFBOHl (ORCPT ); Sat, 2 Jun 2018 10:07:41 -0400 Received: by mail-oi0-f66.google.com with SMTP id b130-v6so24800727oif.12; Sat, 02 Jun 2018 07:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=BSYfWHr7ORd4unPN87OvpdrinUbjqAjZjOvr2/EBX10=; b=izhakypAZQ6GJAIECBuvnrPqfTwNw+KuDHvrPnuAA9yO2GRxIyWjYwyU1FsH2DjkGE uj1gKi/j0iVAkF6RpWqNEWbrrNeTW4QjlUxZ2Ix7KLRXmdu+cz+4VqUZ+uKroQFlgLxF a47Sb1GhCz2gISWGR2wxXe+tYObQQcjz1wGiSFcCKSYZjZ/+Y+sICjttpJ2Gw9SL5LpS p3Y1q8lx/0kLbgvd5nKnsc1PoVl50SZG9Qx1wQckUgfcQsz3f06wse5OTldlcTohafLa rSwuJIr8QpwG8CPwluLP38g2jsHBIzxvf5Zoc0zm5mE/lebRxmuNxytNBHRNHxSy4rX6 BGEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=BSYfWHr7ORd4unPN87OvpdrinUbjqAjZjOvr2/EBX10=; b=FVHNqTjoSEIGcj5343QK8NmCVtn4GU7p2DIm3MAYEuDcY2BcnwSTx79w5lw+XdTjXo H/lFyKGbEd1iqVJjiEHYMBcwPh0FT+H3nBYZS9zDwuRg4usEmWpN7jVhQnPgA0EORlaG 49d9p7UfPNsEetN+ZtVFKzaL+Ay+2M5DUBtygcS18C95pkEWDZAJ5im+qVfPN4vuS0mV tzCKW7IrPJN9Z3+jfLpgkSBrTfiQFQqiK2lw5yS3pHfI5KXMFrZ1fOc/GGiEIIJQo5nX PnVIYq4cLSYmC9nCXxCdb5iZdyQ/xCvcDEhS7NcY2ghUDokRbzOYWMiiVNMVjmpKr8Qx xgHA== X-Gm-Message-State: APt69E1liXMRl8XnHyKFTv40F2ETE0LiVA23HomICnqlp2m72I3AAmnT u5OsoRvp4r+2Cdf7Y/oPq/UaRW9DahJmgd0LJ1E= X-Received: by 2002:aca:3a45:: with SMTP id h66-v6mr3124909oia.336.1527948461073; Sat, 02 Jun 2018 07:07:41 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:4c14:0:0:0:0:0 with HTTP; Sat, 2 Jun 2018 07:07:40 -0700 (PDT) In-Reply-To: References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> From: Fabio Estevam Date: Sat, 2 Jun 2018 11:07:40 -0300 Message-ID: Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates To: Michael Nazzareno Trimarchi Cc: Stefan Wahren , Rob Herring , Fabio Estevam , Mark Rutland , Anson Huang , Matteo Lisi , Shawn Guo , Sascha Hauer , Michael Turquette , Stephen Boyd , linux-clk , NXP Linux Team , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Michael, On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi wrote: > ull is a preatty new platform so one board was listed. Are you sure > that we need? There are several imx6ul based dts in mainline and it is better if we can avoid dtb breakage when possible. In this case we can avoid the dtb breakage by adding the new clock definitions at the end of the file, just like we do for all the other imx devices.