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[209.132.180.67]) by mx.google.com with ESMTP id f1-v6si47954886plf.453.2018.06.04.06.57.33; Mon, 04 Jun 2018 06:57:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jiBlvOqP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753449AbeFDN5D (ORCPT + 99 others); Mon, 4 Jun 2018 09:57:03 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:9251 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753188AbeFDN46 (ORCPT ); Mon, 4 Jun 2018 09:56:58 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w54DuZTc023351; Mon, 4 Jun 2018 08:56:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528120596; bh=GmwF6IiPSVlsaTdyLKEBfSdn1XgE0FHMa7FyHq9DDog=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=jiBlvOqP5hFYJ4DXYcwqmHczbER4SL38qiMHTJSuLKwVBqvxk/ETZ7B9JDN1JQzJQ NxWv2u0uPt6FZ1nieAgnaFK1NUSi9udJnjVOkKuJnGVmiTfEkgazaQB0/Uf9P5rcZ9 4t4xiuKQ3uo9E0f0O6BEQOyke9zkNijH3GdskSxA= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w54DuZ06013188; Mon, 4 Jun 2018 08:56:35 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 4 Jun 2018 08:56:35 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 4 Jun 2018 08:56:35 -0500 Received: from [172.24.190.215] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w54DuWER020400; Mon, 4 Jun 2018 08:56:32 -0500 Subject: Re: [PATCH v2 3/6] clk: ti: dra7: Add clkctrl clock data for the mcan clocks To: Tony Lindgren CC: Tero Kristo , Rob Herring , , , , , , , References: <20180530141133.3711-1-faiz_abbas@ti.com> <20180530141133.3711-4-faiz_abbas@ti.com> <20180531040350.GA25132@rob-hp-laptop> <678ef467-a235-91db-8bae-f249ad98eac8@ti.com> <20180601142613.GU5705@atomide.com> From: Faiz Abbas Message-ID: <6df7e0cd-5574-aa19-6c99-4438e5e377e0@ti.com> Date: Mon, 4 Jun 2018 19:28:01 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180601142613.GU5705@atomide.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Friday 01 June 2018 07:56 PM, Tony Lindgren wrote: > * Faiz Abbas [180601 06:49]: >> Hi, >> >> On Thursday 31 May 2018 06:59 PM, Tero Kristo wrote: >>> On 31/05/18 13:14, Faiz Abbas wrote: >>>> Hi, >>>> >>>> On Thursday 31 May 2018 09:33 AM, Rob Herring wrote: >>>>> On Wed, May 30, 2018 at 07:41:30PM +0530, Faiz Abbas wrote: >>>>>> Add clkctrl data for the m_can clocks and register it within the >>>> ... >>>>>>   diff --git a/include/dt-bindings/clock/dra7.h >>>>>> b/include/dt-bindings/clock/dra7.h >>>>>> index 5e1061b15aed..d7549c57cac3 100644 >>>>>> --- a/include/dt-bindings/clock/dra7.h >>>>>> +++ b/include/dt-bindings/clock/dra7.h >>>>>> @@ -168,5 +168,6 @@ >>>>>>   #define DRA7_COUNTER_32K_CLKCTRL    DRA7_CLKCTRL_INDEX(0x50) >>>>>>   #define DRA7_UART10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x80) >>>>>>   #define DRA7_DCAN1_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88) >>>>>> +#define DRA7_ADC_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0) >>>>> >>>>> ADC and mcan are the same thing? >>>>> >>>> >>>> The register to control MCAN clocks is called ADC_CLKCTRL, Yes. >>> >>> Is there any reason for this or is that just a documentation bug? >>> >> >> Looks like they meant to have an ADC in dra74 or dra72 but decided >> against it and then many years later used the same registers for MCAN >> instead. You can see ADC_CLKCTRL exists in dra72 TRM but is explicitly >> disabled. >> >> http://www.ti.com/lit/ug/spruic2b/spruic2b.pdf pg:1524 > > How about make add also something like to dra7.h: > > #define DRA7_MCAN_CLKCTRL DRA7_ADC_CLKCTRL > > And you can add a comment to the dts file to avoid people > getting confused with this constantly. > I would prefer to follow the TRM so that people don't look for registers that don't exist at all. Thanks, Faiz