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[209.132.180.67]) by mx.google.com with ESMTP id l16-v6si36771129pgc.177.2018.06.04.16.18.00; Mon, 04 Jun 2018 16:18:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=OGO6b5zF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752104AbeFDXR2 (ORCPT + 99 others); Mon, 4 Jun 2018 19:17:28 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:44969 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751198AbeFDXRZ (ORCPT ); Mon, 4 Jun 2018 19:17:25 -0400 Received: by mail-pf0-f196.google.com with SMTP id h12-v6so217548pfk.11 for ; Mon, 04 Jun 2018 16:17:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=6iL2jXAqYe3Ppld/NnkqqeLIQMVdqMLJYr6g6gt2yX8=; b=OGO6b5zFqE2unB+uVN0XapC3PDInnncaYDuCdQA4eh1J8YgTNICfAQ1BEgh9UGteLh essBoF6NAt/Qvn8q1U7cF3I2f0sJhaD+fRizMQeVl5eDUVksIV2jSML7HTEWx+9UqdC9 BgsoFZdFF8d3g3HC83Q+b0FL6ot4XS0ZlgDDHeYng9T9jT6mrEYwJNsRqwCp/ft7zAZk Ko017zLWmcey1+T1ySumm7JXIhIZu6bGSbG+8ArHPqGNiRMJYCzvZEGrtF2JMwe0epBu BBPRiTCUjUgMZ1aq0galHLl13dnFDmWGPavvgNBQza0IGtsjECozc3yLHlz1mb0N2nQH kp+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=6iL2jXAqYe3Ppld/NnkqqeLIQMVdqMLJYr6g6gt2yX8=; b=IniB9StI5eiGTI8TWBJO7+euidkjPUNSHBafyPkcxYkREnylYdV+d5PYPZuooWPv6w qXqH++cWz1fvUVxtLri1o/xPKDBoD9aABNNhZ5o//7tjhfD9Badb5XEgC+BtzDvkHE+X He5fsm2O33A/PVN4IlpsAWuNN1ZttoBg0y4bURcfWztMeEYWR59n/c3vDY8AV8jKbbXD h8hhgOEu853S4OE8HCfdWMiNkr+MJTHFRDV/YrwF4UPRWTTEmFoJl0qgXNbkdPusfesP lPMuqHhse+pJ1RUzucZCrdB32xMkXBjvUUkZjJbQ/qXQU/tf7dao5ZyMYyGmupNNX5Nt wYnw== X-Gm-Message-State: ALKqPwcumKQyoiK+3gMc/bdSOu8gMKkyui3IdUCHcIxJ1eVTf9m1Scna 2pV0L6fWRWRmY4XA4V69jSz0u7V41Hs= X-Received: by 2002:a63:a702:: with SMTP id d2-v6mr19165063pgf.246.1528154244706; Mon, 04 Jun 2018 16:17:24 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id z28-v6sm47453795pfl.169.2018.06.04.16.17.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 16:17:24 -0700 (PDT) Date: Mon, 04 Jun 2018 16:17:24 -0700 (PDT) X-Google-Original-Date: Mon, 04 Jun 2018 15:52:12 PDT (-0700) Subject: Re: [PATCHv2 13/16] atomics/treewide: make test ops optional In-Reply-To: <20180529154346.3168-14-mark.rutland@arm.com> CC: linux-kernel@vger.kernel.org, mark.rutland@arm.com, boqun.feng@gmail.com, Will Deacon From: Palmer Dabbelt To: mark.rutland@arm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 29 May 2018 08:43:43 PDT (-0700), mark.rutland@arm.com wrote: > Some of the atomics return the result of a test applied after the atomic > operation, and almost all architectures implement these as trivial > wrappers around the underlying atomic. Specifically: > > * _inc_and_test(v) is (_inc_return(v) == 0) > > * _dec_and_test(v) is (_dec_return(v) == 0) > > * _sub_and_test(i, v) is (_sub_return(i, v) == 0) > > * _add_negative(i, v) is (_add_return(i, v) < 0) > > Rather than have these definitions duplicated in all architectures, with > minor inconsistencies in formatting and documentation, let's make these > operations optional, with default fallbacks as above. Implementations > must now provide a preprocessor symbol. > > The instrumented atomics are updated accordingly. > > Both x86 and m68k have custom implementations, which are left as-is, > given preprocessor symbols to avoid being overridden. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Acked-by: Geert Uytterhoeven > Acked-by: Peter Zijlstra (Intel) > Cc: Boqun Feng > Cc: Will Deacon > --- > arch/alpha/include/asm/atomic.h | 12 --- > arch/arc/include/asm/atomic.h | 10 --- > arch/arm/include/asm/atomic.h | 9 --- > arch/arm64/include/asm/atomic.h | 8 -- > arch/h8300/include/asm/atomic.h | 5 -- > arch/hexagon/include/asm/atomic.h | 5 -- > arch/ia64/include/asm/atomic.h | 23 ------ > arch/m68k/include/asm/atomic.h | 4 + > arch/mips/include/asm/atomic.h | 84 -------------------- > arch/parisc/include/asm/atomic.h | 22 ------ > arch/powerpc/include/asm/atomic.h | 30 -------- > arch/riscv/include/asm/atomic.h | 46 ----------- > arch/s390/include/asm/atomic.h | 8 -- > arch/sh/include/asm/atomic.h | 4 - > arch/sparc/include/asm/atomic_32.h | 15 ---- > arch/sparc/include/asm/atomic_64.h | 20 ----- > arch/x86/include/asm/atomic.h | 4 + > arch/x86/include/asm/atomic64_32.h | 54 ------------- > arch/x86/include/asm/atomic64_64.h | 4 + > arch/xtensa/include/asm/atomic.h | 42 ---------- > include/asm-generic/atomic-instrumented.h | 24 ++++++ > include/asm-generic/atomic.h | 9 --- > include/asm-generic/atomic64.h | 4 - > include/linux/atomic.h | 124 ++++++++++++++++++++++++++++++ > 24 files changed, 160 insertions(+), 410 deletions(-) > [...] > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index d959bbaaad41..68eef0a805ca 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -209,36 +209,6 @@ ATOMIC_OPS(xor, xor, i) > #undef ATOMIC_FETCH_OP > #undef ATOMIC_OP_RETURN > > -/* > - * The extra atomic operations that are constructed from one of the core > - * AMO-based operations above (aside from sub, which is easier to fit above). > - * These are required to perform a full barrier, but they're OK this way > - * because atomic_*_return is also required to perform a full barrier. > - * > - */ > -#define ATOMIC_OP(op, func_op, comp_op, I, c_type, prefix) \ > -static __always_inline \ > -bool atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ > -{ \ > - return atomic##prefix##_##func_op##_return(i, v) comp_op I; \ > -} > - > -#ifdef CONFIG_GENERIC_ATOMIC64 > -#define ATOMIC_OPS(op, func_op, comp_op, I) \ > - ATOMIC_OP(op, func_op, comp_op, I, int, ) > -#else > -#define ATOMIC_OPS(op, func_op, comp_op, I) \ > - ATOMIC_OP(op, func_op, comp_op, I, int, ) \ > - ATOMIC_OP(op, func_op, comp_op, I, long, 64) > -#endif > - > -ATOMIC_OPS(add_and_test, add, ==, 0) > -ATOMIC_OPS(sub_and_test, sub, ==, 0) > -ATOMIC_OPS(add_negative, add, <, 0) > - > -#undef ATOMIC_OP > -#undef ATOMIC_OPS > - > #define ATOMIC_OP(op, func_op, I, c_type, prefix) \ > static __always_inline \ > void atomic##prefix##_##op(atomic##prefix##_t *v) \ > @@ -315,22 +285,6 @@ ATOMIC_OPS(dec, add, +, -1) > #undef ATOMIC_FETCH_OP > #undef ATOMIC_OP_RETURN > > -#define ATOMIC_OP(op, func_op, comp_op, I, prefix) \ > -static __always_inline \ > -bool atomic##prefix##_##op(atomic##prefix##_t *v) \ > -{ \ > - return atomic##prefix##_##func_op##_return(v) comp_op I; \ > -} > - > -ATOMIC_OP(inc_and_test, inc, ==, 0, ) > -ATOMIC_OP(dec_and_test, dec, ==, 0, ) > -#ifndef CONFIG_GENERIC_ATOMIC64 > -ATOMIC_OP(inc_and_test, inc, ==, 0, 64) > -ATOMIC_OP(dec_and_test, dec, ==, 0, 64) > -#endif > - > -#undef ATOMIC_OP > - > /* This is required to provide a full barrier on success. */ > static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) > { Acked-by: Palmer Dabbelt