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[209.132.180.67]) by mx.google.com with ESMTP id a21-v6si23387940pls.237.2018.06.04.16.25.23; Mon, 04 Jun 2018 16:25:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=Qfn16G1F; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752164AbeFDXYt (ORCPT + 99 others); Mon, 4 Jun 2018 19:24:49 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:38090 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752137AbeFDXYr (ORCPT ); Mon, 4 Jun 2018 19:24:47 -0400 Received: by mail-pf0-f195.google.com with SMTP id b74-v6so232489pfl.5 for ; Mon, 04 Jun 2018 16:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=KiqGxxrGgjONxfA1fauqlgVcYyxq5fpDIRR+bSFp+cY=; b=Qfn16G1Fl0gQ66RSwaUVGlyGFrL1ufp1slcBH3fIkFXE7+qEaMA4Kz0CGVzjv/Xxfp CwwWOz3pozRTm91zs1E1WXzni4/7iOztj8shCCKJlhD4vI6923AGqeMETFLQwrpC7JIo FlvLL378EL5OilIqbOhXMOWfbojRFCoCF2El9ObGMH1pwkMPcrL3PzCAsCN4UivjhPRn Ff+SEYl7E7ZpduFApi89j5SCfphMcMqACTpuYsZV+xzkraxHV6JicOiSvNB1gOQm1phR Wp/cmtln0LuRUIP1VZ9X+4D+fVGXdFzc8qaUfEQXVN9NvHCDgKKH1fSRD83soFdtZuf1 dSAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=KiqGxxrGgjONxfA1fauqlgVcYyxq5fpDIRR+bSFp+cY=; b=NQtqQkm1SpLiqUFbLuTCV+mct+eWPkG3wGSqghu93Q/7kluB6L6BRgntNrUXnVGDGI e0+Uzw2IR+CIU7Xyj3N05IcrMQ9Dv/bJoGboqBNHJl9RtLTwBwBv5OS+qeIEHyPW9w5d dFGeliswCtE8VnWaCFlkdNmWrcAm5Ir8AYE68gi3nlERIVcYJcRvmzFjyqKwKJRWQpCV cANb4wKx0XdkyuIWFxZ88qOKY5JS90QBVCqVzWe5OHJR97+MPJ/yLDjDhMbfYwBiWwPM G2hDd+qc9yfrIvaG7WFoSi7bC7p4eUkS2OCxaSiz+Qo7S8aMwbsGaAbPTl31p9k/5q5o 5Znw== X-Gm-Message-State: APt69E1cXhAUwZpHagJ9mAmrIA2oC7yovjJmErFZ4vs0iMBhJWRl6S+E NmD2A4xqUG4mFMQPQKdGeoRFn6KNMRc= X-Received: by 2002:a65:58cc:: with SMTP id e12-v6mr4884540pgu.445.1528154686546; Mon, 04 Jun 2018 16:24:46 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id u18-v6sm5128451pfm.152.2018.06.04.16.24.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 16:24:46 -0700 (PDT) Date: Mon, 04 Jun 2018 16:24:46 -0700 (PDT) X-Google-Original-Date: Mon, 04 Jun 2018 16:20:45 PDT (-0700) Subject: Re: [PATCHv2 02/16] atomics/treewide: remove redundant atomic_inc_not_zero() definitions In-Reply-To: <20180529154346.3168-3-mark.rutland@arm.com> CC: linux-kernel@vger.kernel.org, mark.rutland@arm.com, boqun.feng@gmail.com, Will Deacon From: Palmer Dabbelt To: mark.rutland@arm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 29 May 2018 08:43:32 PDT (-0700), mark.rutland@arm.com wrote: > When atomic_inc_not_zero(v) isn't defined, will define > it as falling back to atomic_add_unless((v), 1, 0), so there's no need > for arch code to do so. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Acked-by: Peter Zijlstra (Intel) > Cc: Boqun Feng > Cc: Will Deacon > --- > arch/arc/include/asm/atomic.h | 2 -- > arch/hexagon/include/asm/atomic.h | 2 -- > arch/riscv/include/asm/atomic.h | 9 --------- > 3 files changed, 13 deletions(-) > [...] > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index 739e810c857e..0e27e050ba14 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -375,15 +375,6 @@ static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u) > } > #endif > > -/* > - * The extra atomic operations that are constructed from one of the core > - * LR/SC-based operations above. > - */ > -static __always_inline int atomic_inc_not_zero(atomic_t *v) > -{ > - return atomic_fetch_add_unless(v, 1, 0); > -} > - > #ifndef CONFIG_GENERIC_ATOMIC64 > static __always_inline long atomic64_inc_not_zero(atomic64_t *v) > { Acked-by: Palmer Dabbelt Thanks!