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[209.132.180.67]) by mx.google.com with ESMTP id j7-v6si19924131plk.334.2018.06.04.16.25.35; Mon, 04 Jun 2018 16:25:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=buAx7MMS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752186AbeFDXY7 (ORCPT + 99 others); Mon, 4 Jun 2018 19:24:59 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36931 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751625AbeFDXYt (ORCPT ); Mon, 4 Jun 2018 19:24:49 -0400 Received: by mail-pf0-f195.google.com with SMTP id e9-v6so232035pfi.4 for ; Mon, 04 Jun 2018 16:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=vA0Jg3UrwkYRrjvHmf7scotU3D79pcUQM9McacEgFsA=; b=buAx7MMSWC4vbpoHKFOUgpmzlCXv1wAUB06fwBv+5H9Zg5iaiD5F3+REYMeMe2kBya VhaaaCGDBkEwg6kuO1CPfGKjLpc+iQbIAoLTH59YjT5hdfAYaly70YdLmV+xQdf3pNzR QKFqpCmrIT/vxZ3O5IZ2PzRw4hKdoSOWFNUiMuGpQ6zuu1UP8sTLQK0Ctgd8/n90+lu9 OCptTVx+wqZF/VVpus18zU0wM+VRw+d1PG6GhqRtEzXwyGpBrfSlocMIf/kZ+BH6j4cN ZVdjSAKcqcZPibiTtoPoHR1Uw/ldcJep2DwkaWLgm+cWDp6c0YI0XSEIlkuFl2o58/hA J6Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=vA0Jg3UrwkYRrjvHmf7scotU3D79pcUQM9McacEgFsA=; b=ZUoHnH0VptpH/TvAzPxlNf9GO2EiEpNgbP711InOTUWeHud2WEdJqxTV8lCD40OnKl +y+YkOKuTfc/KJ3za4Um42lUi4+QzMMF+rmOMBtznVo30XJwj3inZ8myf29LUeNrVVNV 7tp22OBAXebq80FzMFZJk1cPhBXjdoUq+uN6dicXM0H7M3JvPuDIZWQVnKqMahknHkpI CYlcpYXo1fMhIDC+B6Oilovzw4lsQBG7e6ZszrdW7+N6HUTv1AFWvh0Y3mHyp8zpIx7Y 7w7aSGU5qrbztSIzotfuboWIhs5159eEX1n7fQIX6kwGuhUUV5rnexZoWQOoe9XbCyYO yuUQ== X-Gm-Message-State: ALKqPwc+Q5SidL8Ixor9f/vIUfGedgGGQi9zfsKN/sLFLzg5tmUnyM4/ /hb0vK4aMcWQJT5qUi3Vpbc2EP8tuXQ= X-Received: by 2002:a63:83c3:: with SMTP id h186-v6mr18368578pge.298.1528154688180; Mon, 04 Jun 2018 16:24:48 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id b74-v6sm59488357pfl.138.2018.06.04.16.24.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 16:24:47 -0700 (PDT) Date: Mon, 04 Jun 2018 16:24:47 -0700 (PDT) X-Google-Original-Date: Mon, 04 Jun 2018 16:21:55 PDT (-0700) Subject: Re: [PATCHv2 04/16] atomics/treewide: make atomic_fetch_add_unless() optional In-Reply-To: <20180529154346.3168-5-mark.rutland@arm.com> CC: linux-kernel@vger.kernel.org, mark.rutland@arm.com, boqun.feng@gmail.com, Will Deacon , vgupta@synopsys.com From: Palmer Dabbelt To: mark.rutland@arm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 29 May 2018 08:43:34 PDT (-0700), mark.rutland@arm.com wrote: > Several architectures these have a near-identical implementation based > on atomic_read() and atomic_cmpxchg() that we can instead define in > , so let's do so, using something close to the existing > x86 implementation with try_cmpxchg(). > > Where an architecture provides its own atomic_fetch_add_unless(), it > must define a preprocessor symbol for it. The instrumented atomics are > updated accordingly. > > Note that arch/arc's existing atomic_fetch_add_unless() had redundant > barriers, as these are already present in its atomic_cmpxchg() > implementation. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Reviewed-by: Geert Uytterhoeven > Acked-by: Geert Uytterhoeven > Acked-by: Peter Zijlstra (Intel) > Cc: Boqun Feng > Cc: Will Deacon > Cc: Vineet Gupta > --- > arch/alpha/include/asm/atomic.h | 2 +- > arch/arc/include/asm/atomic.h | 28 ---------------------------- > arch/arm/include/asm/atomic.h | 11 +---------- > arch/arm64/include/asm/atomic.h | 1 - > arch/h8300/include/asm/atomic.h | 1 + > arch/hexagon/include/asm/atomic.h | 1 + > arch/ia64/include/asm/atomic.h | 16 ---------------- > arch/m68k/include/asm/atomic.h | 15 --------------- > arch/mips/include/asm/atomic.h | 24 ------------------------ > arch/parisc/include/asm/atomic.h | 24 ------------------------ > arch/powerpc/include/asm/atomic.h | 1 + > arch/riscv/include/asm/atomic.h | 1 + > arch/s390/include/asm/atomic.h | 15 --------------- > arch/sh/include/asm/atomic.h | 25 ------------------------- > arch/sparc/include/asm/atomic_32.h | 2 ++ > arch/sparc/include/asm/atomic_64.h | 15 --------------- > arch/x86/include/asm/atomic.h | 21 --------------------- > arch/xtensa/include/asm/atomic.h | 24 ------------------------ > include/asm-generic/atomic-instrumented.h | 4 +++- > include/asm-generic/atomic.h | 11 ----------- > include/linux/atomic.h | 23 +++++++++++++++++++++++ > 21 files changed, 34 insertions(+), 231 deletions(-) > [...] > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index 18259e90f57e..5f161daefcd2 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -349,6 +349,7 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) > : "memory"); > return prev; > } > +#define atomic_fetch_add_unless atomic_fetch_add_unless > > #ifndef CONFIG_GENERIC_ATOMIC64 > static __always_inline long __atomic64_add_unless(atomic64_t *v, long a, long u) Acked-by: Palmer Dabbelt Thanks!