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[209.132.180.67]) by mx.google.com with ESMTP id z28-v6si20837526pge.483.2018.06.04.16.25.57; Mon, 04 Jun 2018 16:26:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=W0E713dT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752143AbeFDXYr (ORCPT + 99 others); Mon, 4 Jun 2018 19:24:47 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:46211 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751625AbeFDXYp (ORCPT ); Mon, 4 Jun 2018 19:24:45 -0400 Received: by mail-pf0-f195.google.com with SMTP id q1-v6so222142pff.13 for ; Mon, 04 Jun 2018 16:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=vbh3i7evQHoveMvdT60Yd/YGFTJJrLw3iYbeW+dvnYs=; b=W0E713dTAntwCPuEMX6p/E5TyXOuFSTAcoQ7ZYSgeyQTD7F9cHwFZMvC+fLiIod8IU dqMgTENg8TE5De5U2yW/V4V9FsUlAnwZUk/1v7nVJawyHb254BTnC7633/7rJhHNMS31 wcPF8P7YOs4TLBZwppHVKoTZGti+U3RLJTcZ/OGgrZTO8qY36KbSWSPSq3zgaXVtKa/o P1ZUlLQXamavA4DFjx6ZafXXSkntxw2RRfFlYT8xffX5Txw9OCWwulDjP3uvvAEDkgO2 ArUk4RfP4AtN0xoQPPQfFwTWbicDqLnENl0h3ABOymE8rSA4wPE4PblvrIFsOWnPQUcA Rr2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=vbh3i7evQHoveMvdT60Yd/YGFTJJrLw3iYbeW+dvnYs=; b=UIJBIMeuK62OQ91ltUnJoqid6Mqq0sdHHQOrIwHoBAK/c6Fo1D56bpaKi3p1FdQypO MdIOwvWPz09kX+7k8wDBubrrk4eO0TII1kju5LyDmNUCc1KSxbPezU/u4D9ng7F3f25f ynjefyV2K+5yicj8CHXa7AzCvFA3cMHhSNwMFPRgPe7z5+1uJZvJZDNwzGVldi/DWCiI JjhCPHpQ6DrBfklfG/Lt5AGshJzQkwAWmgQccSI9GAa4pam+bIo7OouKLMcv32Os2VTr RNF3NCjh9niyHISmPvb5R8yVKWfJcwp7acvFVc7zmUg3z4z6SVilyglw8QiQl1nqPWln s8sA== X-Gm-Message-State: ALKqPwf/UFtN1TPOnRpT4RqUdguiLFXmRrdS0ICuZYktV8uJYbiu8mQV Bf26MPbnappBDIZBtE/9TB3E+CKRBek= X-Received: by 2002:a63:7f51:: with SMTP id p17-v6mr18591221pgn.36.1528154685159; Mon, 04 Jun 2018 16:24:45 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c17-v6sm45048043pgw.11.2018.06.04.16.24.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 16:24:44 -0700 (PDT) Date: Mon, 04 Jun 2018 16:24:44 -0700 (PDT) X-Google-Original-Date: Mon, 04 Jun 2018 16:20:06 PDT (-0700) Subject: Re: [PATCHv2 01/16] atomics/treewide: s/__atomic_add_unless/atomic_fetch_add_unless/ In-Reply-To: <20180529154346.3168-2-mark.rutland@arm.com> CC: linux-kernel@vger.kernel.org, mark.rutland@arm.com, boqun.feng@gmail.com, Will Deacon From: Palmer Dabbelt To: mark.rutland@arm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 29 May 2018 08:43:31 PDT (-0700), mark.rutland@arm.com wrote: > While __atomic_add_unless was originally intended as a building-block > for atomic_add_unless, it's now used in a number of places around the > kernel. It's the only common atomic operation named __atomic*(), rather > than atomic_*(), and for consistency it would be better named > atomic_fetch_add_unless(). > > This lack of consistency is slightly confusing, and gets in the way of > scripting atomics. Given that, let's clean things up and promote it to > an offical part of the atomics API, in the form of > atomic_fetch_add_unless(). > > This patch converts definitions and uses over to the new name, including > the instrumented version, using the following script: > > ---- > git grep -w __atomic_add_unless | while read line; do > sed -i '{s/\<__atomic_add_unless\>/atomic_fetch_add_unless/}' "${line%%:*}"; > done > git grep -w __arch_atomic_add_unless | while read line; do > sed -i '{s/\<__arch_atomic_add_unless\>/arch_atomic_fetch_add_unless/}' "${line%%:*}"; > done > ---- > > Note that we do not have atomic{64,_long}_fetch_add_unless(), which will > be introduced by later patches. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Acked-by: Geert Uytterhoeven > Acked-by: Peter Zijlstra (Intel) > Cc: Boqun Feng > Cc: Will Deacon > --- > arch/alpha/include/asm/atomic.h | 4 ++-- > arch/arc/include/asm/atomic.h | 4 ++-- > arch/arm/include/asm/atomic.h | 4 ++-- > arch/arm64/include/asm/atomic.h | 2 +- > arch/h8300/include/asm/atomic.h | 2 +- > arch/hexagon/include/asm/atomic.h | 4 ++-- > arch/ia64/include/asm/atomic.h | 2 +- > arch/m68k/include/asm/atomic.h | 2 +- > arch/mips/include/asm/atomic.h | 4 ++-- > arch/openrisc/include/asm/atomic.h | 4 ++-- > arch/parisc/include/asm/atomic.h | 4 ++-- > arch/powerpc/include/asm/atomic.h | 8 ++++---- > arch/riscv/include/asm/atomic.h | 4 ++-- > arch/s390/include/asm/atomic.h | 2 +- > arch/sh/include/asm/atomic.h | 4 ++-- > arch/sparc/include/asm/atomic_32.h | 2 +- > arch/sparc/include/asm/atomic_64.h | 2 +- > arch/sparc/lib/atomic32.c | 4 ++-- > arch/x86/include/asm/atomic.h | 4 ++-- > arch/xtensa/include/asm/atomic.h | 4 ++-- > drivers/block/rbd.c | 2 +- > drivers/infiniband/core/rdma_core.c | 2 +- > fs/afs/rxrpc.c | 2 +- > include/asm-generic/atomic-instrumented.h | 4 ++-- > include/asm-generic/atomic.h | 4 ++-- > include/linux/atomic.h | 2 +- > kernel/bpf/syscall.c | 4 ++-- > net/rxrpc/call_object.c | 2 +- > net/rxrpc/conn_object.c | 4 ++-- > net/rxrpc/local_object.c | 2 +- > net/rxrpc/peer_object.c | 2 +- > 31 files changed, 50 insertions(+), 50 deletions(-) > [...] > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index 855115ace98c..739e810c857e 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -332,7 +332,7 @@ ATOMIC_OP(dec_and_test, dec, ==, 0, 64) > #undef ATOMIC_OP > > /* This is required to provide a full barrier on success. */ > -static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u) > +static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) > { > int prev, rc; > > @@ -381,7 +381,7 @@ static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u) > */ > static __always_inline int atomic_inc_not_zero(atomic_t *v) > { > - return __atomic_add_unless(v, 1, 0); > + return atomic_fetch_add_unless(v, 1, 0); > } > > #ifndef CONFIG_GENERIC_ATOMIC64 > diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h > index 4b55532f15c4..c2858cdd8c29 100644 > --- a/arch/s390/include/asm/atomic.h > +++ b/arch/s390/include/asm/atomic.h > @@ -90,7 +90,7 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) > return __atomic_cmpxchg(&v->counter, old, new); > } > > -static inline int __atomic_add_unless(atomic_t *v, int a, int u) > +static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) > { > int c, old; > c = atomic_read(v); Acked-by: Palmer Dabbelt Thanks!