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[209.132.180.67]) by mx.google.com with ESMTP id j33-v6si47904994pld.151.2018.06.04.18.20.18; Mon, 04 Jun 2018 18:20:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=ZuFUVzf+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751617AbeFEBSx (ORCPT + 99 others); Mon, 4 Jun 2018 21:18:53 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:44933 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751578AbeFEBSv (ORCPT ); Mon, 4 Jun 2018 21:18:51 -0400 Received: by mail-pf0-f195.google.com with SMTP id h12-v6so350900pfk.11 for ; Mon, 04 Jun 2018 18:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=rPD5dD/V8CSxrfwxjghvYi0/70PVgvG+a4TryRLFmjw=; b=ZuFUVzf+Xl/tLhz0OdSmT3bH2Ln1iCIfioVMx3epUQjS/HjIg1kM3fkaTojmdzE3SX 2Jq7tt5ZcxFhAX/uvYsMV4kA5DGn968pfY0/CtAdFVO894FR/X0Qq2XMevOa7FlhSCii XsT0ux6JnBGXNjK0UPb7euZ00+oxQb2Si+fVi94MlKc2Xoe7PB5JjDBU0H0R2imraZ3R 7x1SEZKPhpLIDC1df/pBQy+5JinQi4SLR6WBelHjoYN4Ka1UpW+qIz0DyM/wRSgOTc/u kLQK1nkyc69fdCQOu3dg9Bz4YUEnVT1qJhGIaRT+mGQqqI3248DoBAygiGYwpAJ51fwQ mW6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=rPD5dD/V8CSxrfwxjghvYi0/70PVgvG+a4TryRLFmjw=; b=hPCHFQhXOx584BUMwkcv/Nr/WruUYkRCteHr2XHrSJWqko0xRV2VJrU8qgls15jd5B hv0QmY75ymn9N47XARyANEe3/2WakiRN3QCP443CfYbJWbfxFNU8S44szWjM2cOlqBcW bO745JjAJ2XxNQpDBLqf/Ti3G4rx9uDZtA3sk68V3942/DaHKPA0YwgyxP93pE/5UjIz LdGXwyjgS7OlvtDQajzk6idjnlwfAMfrIPTBTgY2426vGW8PcfgESXI4mUQV05DplzjV T81//3ry/XGkJlqmvIIfFkYwuiBtoXYW6p3FXUk1jtgnIvNLaRpz8U99tfDYtdqdLbr7 PUDg== X-Gm-Message-State: ALKqPwfEU36iqY27d0Yo+3/x/tBWQcUQddx8IgiGNP6UoPmpeyft3fIi vjuHPgw+37SjTFu684mSUZ0fOAx7+UE= X-Received: by 2002:a62:d2c3:: with SMTP id c186-v6mr19241194pfg.44.1528161531125; Mon, 04 Jun 2018 18:18:51 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id m1-v6sm13702091pfh.155.2018.06.04.18.18.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 18:18:50 -0700 (PDT) Date: Mon, 04 Jun 2018 18:18:50 -0700 (PDT) X-Google-Original-Date: Mon, 04 Jun 2018 18:17:03 PDT (-0700) Subject: Re: [PATCH] riscv: pass machine size to sparse In-Reply-To: <20180531153553.kex32gupopdq2nqh@ltop.local> CC: yamada.masahiro@socionext.com, Christoph Hellwig , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, albert@sifive.com, michal.lkml@markovi.net From: Palmer Dabbelt To: luc.vanoostenryck@gmail.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 31 May 2018 08:35:54 PDT (-0700), luc.vanoostenryck@gmail.com wrote: > On Thu, May 31, 2018 at 05:09:21AM -0700, Palmer Dabbelt wrote: >> On Mon, 28 May 2018 23:14:20 PDT (-0700), yamada.masahiro@socionext.com wrote: >> > 2018-05-29 15:11 GMT+09:00 Christoph Hellwig : >> > > On Mon, May 28, 2018 at 06:35:05PM +0200, Luc Van Oostenryck wrote: >> > > > By default, sparse assumes a 64bit machine when compiled on x86-64 >> > > > and 32bit when compiled on anything else. >> > > > >> > > > This can of course create all sort of problems when this doesn't >> > > > correspond to the target's machine size, like issuing false >> > > > warnings like: 'shift too big (32) for type unsigned long' or >> > > > is 64bit while sparse was compiled on a 32bit machine, or worse, >> > > > to not emit legitimate warnings. >> > > > >> > > > Fix this by passing the appropriate -m32/-m64 flag to sparse. >> > > >> > > Can we please move this to the common Kbuild code using the >> > > CONFIG_64BIT syombol? This really should not need boiler plate in >> > > every architecture. >> > >> > >> > I agree. >> > >> > Luc did so for -mbig/little-endian: >> > https://patchwork.kernel.org/patch/10433957/ >> > >> > We should do likewise for -m32/64. >> >> Sorry for being a bit slow here, but I like the idea of making the >> 32/64-bit issue generic as it seems like it'll be necessary for >> every port. > > Sure, Christophe asked it too. > I've sent a new version doing it once and for all for all archs > but I forgot to CC you: > https://lkml.org/lkml/2018/5/30/948 > >> Looking through the patch for big/little-endian I did >> notice: >> >> * RISC-V compilers set "__riscv_xlen" to the length of an X >> (integer) register in bits. >> * RISC-V compilers define "__riscv", and it doesn't appear we inform >> sparse about that. >> >> These two might not be that interesting, but we do already have some >> cases where we're checking for __riscv_xlen in Linux. I've yet to >> successfully use sparse, but adding at least >> >> CHECKFLAGS += -D__riscv >> >> seems reasonable, > > Sure (but I don't see a dependency in the kernel (yet)). > >> and possibly also some sort of >> >> ifeq ($(CONFIG_ARCH_RV64I),y) >> CHECKFLAGS += -D__riscv_xlen=64 >> else >> CHECKFLAGS += -D__riscv_xlen=32 >> fi >> >> might be necessary. > > Yes, this one is really needed. > I'll send a patch for this one and __riscv. > >> We strive to follow the generic rules for >> ABI-related stuff like __LP64__ but I don't think there's any >> generic mapping for XLEN. Similarly there's "__riscv_flen" and >> "__riscv_float_abi_*", but those are less likely to be used by the >> kernel so they're probably not worth worrying about for now. > > Yes, I agree. > Note that sparse will define __LP64__ (and _LP64) when in -m64 mode. > >> There's also a bunch of other RISC-V macros, the only one of which >> we're currently using is "__riscv_muldiv" (and that's in a manner >> that's unlikely to trigger any sort of static analysis). Between a >> lack of Kconfig options and a glibc port we're essentially mandating >> IMA right now, so these probably don't matter. > > Yes, I just saw. I think also it's better to leave it so for now. > And if it becomes more used, then better to infer it from the compiler > than harcoding it. Makes sense. Thanks for the work!