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Subject: Re: [PATCH v2 3/7] PCI: cadence: Update cdns_pcie_ep_raise_irq
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To:     Alan Douglas <adouglas@cadence.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
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        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
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        "jingoohan1@gmail.com" <jingoohan1@gmail.com>,
        "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>
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From:   Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <e9de6853-9c55-2dc9-0de0-0faa075714db@ti.com>
Date:   Tue, 5 Jun 2018 10:51:16 +0530
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On Monday 04 June 2018 08:38 PM, Alan Douglas wrote:
> On 31 May 2018 11:51, Kishon Vijay Abraham I  wrote:
>> Hi Alan,
>>
>> On Thursday 17 May 2018 10:39 PM, Gustavo Pimentel wrote:
>>> Change cdns_pcie_ep_raise_irq() signature, namely the interrupt_num
>>> variable type from u8 to u16 to accommodate 2048 maximum MSI-X
>>> interrupts.
>>>
>>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>>> Acked-by: Alan Douglas <adouglas@cadence.com>
>>
>> Do you want to add MSI-X support to cadence PCIe?
>>
> I do want to add MSI-X support, in fact I have done some tests with a
> modified cadence driver with this set, so plan to submit a patch later.
> 

cool, glad to hear!

Thanks
Kishon