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[209.132.180.67]) by mx.google.com with ESMTP id l12-v6si7957871pfb.69.2018.06.05.01.24.32; Tue, 05 Jun 2018 01:24:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T/S7RjFW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751800AbeFEIYG (ORCPT + 99 others); Tue, 5 Jun 2018 04:24:06 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:43592 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751706AbeFEIYE (ORCPT ); Tue, 5 Jun 2018 04:24:04 -0400 Received: by mail-wr0-f194.google.com with SMTP id d2-v6so1362123wrm.10 for ; Tue, 05 Jun 2018 01:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=+XVyUXHPAvfmZsoUCOMlxUUXrweC6VvTDCfa5cNI3Qc=; b=T/S7RjFWVxxSAyT/1e/1bl32e8Ty4hDsRPgh13Lr/LxRtaEqftA7gSBg4KFRPoq0G1 PezDm14W6mqowu+k1KZR8ZGOEnFOk0VUq4HALqBAiM6xycS3DEOinapXQtAM7HPBvqhR fX6dsUs2T+fFONisyY8JYBQJBteC6nEnLh4T0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=+XVyUXHPAvfmZsoUCOMlxUUXrweC6VvTDCfa5cNI3Qc=; b=gKBuOCgNzeKODTgvvSN5ZjVbRJa5bwrT++wOYs1n+IJisKMP1W1lIBNcUk5XbVzXHa h/d2FZgmxTjeQL9+CcQWFR3isV7I8yGEAmVtPBfI0e1LGsglK/FyiNDRiPrcNZv3Asrk QV+b7f21ELIIlDc4u58wZc9xOFZfR5zqCO4oOlS8qbLdf8uG1PkHks9WTNCQQ7HRPmMm Nnh+EsXhb0nuwF1GGe/C/07Enf+IQIjQS2JbNNccPA+MGOP9YzEXBPA/fVRa6WxsQ2en /TMUJzpyEbOyfYF/N9RaVwkdIalm8Ov3v3TjRuvbu+MgS5mBOWyY11uHY+Ftu7XIwllX IO7Q== X-Gm-Message-State: ALKqPwdC/yucbNQFCzCjUUACYMyaDWZHSdsn9XBAwoK43mCpd+nV/8yJ 1o15obYHLY53/0J/EUbKbj8DAg== X-Received: by 2002:adf:e311:: with SMTP id b17-v6mr19726004wrj.158.1528187043336; Tue, 05 Jun 2018 01:24:03 -0700 (PDT) Received: from dell ([2.31.167.232]) by smtp.gmail.com with ESMTPSA id f18-v6sm20497566wro.1.2018.06.05.01.24.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jun 2018 01:24:02 -0700 (PDT) Date: Tue, 5 Jun 2018 09:24:00 +0100 From: Lee Jones To: Geert Uytterhoeven Cc: Marek Vasut , Linux Kernel Mailing List , Marek Vasut , Geert Uytterhoeven , Mark Brown , Steve Twiss , Wolfram Sang , Linux-Renesas Subject: Re: [PATCH v3 07/10] mfd: da9063: Add custom IRQ map for DA9063L Message-ID: <20180605082400.GQ21163@dell> References: <20180602101155.26375-1-marek.vasut+renesas@gmail.com> <20180602101155.26375-7-marek.vasut+renesas@gmail.com> <20180605074727.GL21163@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 05 Jun 2018, Geert Uytterhoeven wrote: > Hi Lee, > > On Tue, Jun 5, 2018 at 9:47 AM, Lee Jones wrote: > > On Sat, 02 Jun 2018, Marek Vasut wrote: > >> While the datasheet for DA9063L (2v1, 23-Mar-2017) lists the RTC register > >> block, the DA9063L does not have an RTC. Add custom IRQ map for DA9063L to > >> ignore the Alarm and Tick IRQs from the PMIC. > >> > >> Signed-off-by: Marek Vasut > > >> --- a/drivers/mfd/da9063-irq.c > >> +++ b/drivers/mfd/da9063-irq.c > >> @@ -74,8 +74,55 @@ static const struct regmap_irq_chip da9063_irq_chip = { > >> .init_ack_masked = true, > >> }; > >> > >> +static const struct regmap_irq da9063l_irqs[] = { > >> + /* DA9063 event A register */ > >> + REGMAP_IRQ_REG(DA9063_IRQ_ONKEY, DA9063_REG_EVENT_A_OFFSET, DA9063_M_ONKEY), > >> + REGMAP_IRQ_REG(DA9063_IRQ_ADC_RDY, DA9063_REG_EVENT_A_OFFSET, DA9063_M_ADC_RDY), > >> + REGMAP_IRQ_REG(DA9063_IRQ_SEQ_RDY, DA9063_REG_EVENT_A_OFFSET, DA9063_M_SEQ_RDY), > >> + /* DA9063 event B register */ > >> + REGMAP_IRQ_REG(DA9063_IRQ_WAKE, DA9063_REG_EVENT_B_OFFSET, DA9063_M_WAKE), > >> + REGMAP_IRQ_REG(DA9063_IRQ_TEMP, DA9063_REG_EVENT_B_OFFSET, DA9063_M_TEMP), > >> + REGMAP_IRQ_REG(DA9063_IRQ_COMP_1V2, DA9063_REG_EVENT_B_OFFSET, DA9063_M_COMP_1V2), > >> + REGMAP_IRQ_REG(DA9063_IRQ_LDO_LIM, DA9063_REG_EVENT_B_OFFSET, DA9063_M_LDO_LIM), > >> + REGMAP_IRQ_REG(DA9063_IRQ_REG_UVOV, DA9063_REG_EVENT_B_OFFSET, DA9063_M_UVOV), > >> + REGMAP_IRQ_REG(DA9063_IRQ_DVC_RDY, DA9063_REG_EVENT_B_OFFSET, DA9063_M_DVC_RDY), > >> + REGMAP_IRQ_REG(DA9063_IRQ_VDD_MON, DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_MON), > >> + REGMAP_IRQ_REG(DA9063_IRQ_WARN, DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_WARN), > >> + /* DA9063 event C register */ > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI0, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI0), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI1, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI1), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI2, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI2), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI3, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI3), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI4, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI4), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI5, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI5), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI6, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI6), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI7, DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI7), > >> + /* DA9063 event D register */ > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI8, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI8), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI9, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI9), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI10, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI10), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI11, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI11), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI12, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI12), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI13, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI13), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI14, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI14), > >> + REGMAP_IRQ_REG(DA9063_IRQ_GPI15, DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI15), > >> +}; > > > > Same here. Please make checkpatch.pl happen, even if it makes the > > code slightly less readable. > > I beg to disagree: source code should be optimized for reading. > Checkpatch is a hinting tool, not an absolute check. I agree with you to some degree, but as per the Coding Standards we are to use max 80-chars unless it *significantly* reduces readability. Breaking lines into two on a natural break only *slightly* reduces readability, if at all to be frank. We have MACROS which encompass many arguments and we have to draw the line somewhere. I choose 80-chars. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog