Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp771143imm;
        Tue, 5 Jun 2018 04:19:52 -0700 (PDT)
X-Google-Smtp-Source: ADUXVKJeFIU3tc7EKqj9+2DMjpNN6iIxLjC9MX8mnJLxQCP3u3280N4FXqGY3XD4xGcrD0z7p2N6
X-Received: by 2002:a17:902:760e:: with SMTP id k14-v6mr38662pll.310.1528197592214;
        Tue, 05 Jun 2018 04:19:52 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1528197592; cv=none;
        d=google.com; s=arc-20160816;
        b=z5g6UcZWwmRkZW/5hIA4QWlAgovotfpRfKD8GqRWbbVFtUq17ZKJ6Yl88qNfebznL6
         LQ1yhPz2KZpgKX9ej3+rePhOpeiqy6rOKevbKPw+v48uFeX1br1tSMYqI/6uUUHHVNWa
         0efQHkpHv6Y6kxJavsGyJXiY8fKsHYCkiiRCKv2/ytJW/nfc4FcnfyxkPV2nGeIYUhwt
         CYyowuCmK8e638OOXBqrglz+KmlgZTYyHW20wpFYcPpe9MsA8nIW0wioj0opwnSKuKJN
         2gHNrbMdCXq4nXYdh2Oy9QTNi7TvOH8v/a6yCWDt/g3KF+eKVOKvTsKVVp3BvmNmzJWW
         SqWg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:user-agent:in-reply-to
         :content-disposition:mime-version:references:message-id:subject:cc
         :to:from:date:arc-authentication-results;
        bh=Rs3J15hg/fkkFsl6ntylowS9s3Flul5eZoA+fPHJtV0=;
        b=Uj22V0QegV2rgsPahhrXfVlGAk1+hXoKZpEPOa/H9ifuFT/P6CAN+3XAdhsyza0xbN
         aJot1WLpuZXtncGq167kYxp8VUruSTMLXdCQ9z+syMkGfTxtVTef0H0TkXNU6pZ5xO9T
         mLCyFlf+JlSIOejrQhBZm+9UlNuFUgW2R3NeJ9lhBdTSzFvg81IkAKQBtI7/KcJqzC3p
         CnciLgyqbhBcfZF8GTPhr2czZSVS0DqpHbmtSPBJ6PwB4VnKCI+Gp7oAXTycJA6QxDwZ
         aZ7AoZECXbvKahjoo8hGR3YIpBeqvGt+2imxdTULIicN0znkAvrEzesoBh6xlH9dV0Uo
         N/GA==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id n9-v6si3784629plk.310.2018.06.05.04.19.37;
        Tue, 05 Jun 2018 04:19:52 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1751781AbeFELTQ (ORCPT <rfc822;krseo358@gmail.com> + 99 others);
        Tue, 5 Jun 2018 07:19:16 -0400
Received: from hqemgate14.nvidia.com ([216.228.121.143]:10131 "EHLO
        hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1751570AbeFELTO (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 5 Jun 2018 07:19:14 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA)
        id <B5b1671bd0001>; Tue, 05 Jun 2018 04:19:25 -0700
Received: from HQMAIL101.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Tue, 05 Jun 2018 04:19:14 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Tue, 05 Jun 2018 04:19:14 -0700
Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com
 (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 5 Jun
 2018 11:19:13 +0000
Received: by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1002)
        id 1C7C6F80126; Tue,  5 Jun 2018 14:19:11 +0300 (EEST)
Date:   Tue, 5 Jun 2018 14:19:11 +0300
From:   Peter De Schrijver <pdeschrijver@nvidia.com>
To:     Dmitry Osipenko <digetx@gmail.com>
CC:     Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Prashant Gaikwad <pgaikwad@nvidia.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/5] Tegra20 External Memory Controller driver
Message-ID: <20180605111911.GD27696@tbergstrom-lnx.Nvidia.com>
References: <20180603223654.23324-1-digetx@gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20180603223654.23324-1-digetx@gmail.com>
X-NVConfidentiality: public
User-Agent: Mutt/1.5.21 (2010-09-15)
X-Originating-IP: [10.124.1.5]
X-ClientProxiedBy: HQMAIL104.nvidia.com (172.18.146.11) To
 HQMAIL101.nvidia.com (172.20.187.10)
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Jun 04, 2018 at 01:36:49AM +0300, Dmitry Osipenko wrote:
> Hello,
> 
> Couple years ago the Tegra20 EMC driver was removed from the kernel
> due to incompatible changes in the Tegra's clock driver. This patchset
> introduces a modernized EMC driver. Currently the sole purpose of the
> driver is to initialize DRAM frequency to maximum rate during of the
> kernels boot-up. Later we may consider implementing dynamic memory
> frequency scaling, utilizing functionality provided by this driver.
> 
> Changelog:
> 
> v2:
> 	- Minor code cleanups like consistent use of writel_relaxed instead
> 	  of non-relaxed version, reworded error messages, etc.
> 
> 	- Factored out use_pllm_ud bit checking into a standalone patch for
> 	  consistency.
> 
> Dmitry Osipenko (5):
>   dt: bindings: tegra20-emc: Document interrupt property
>   ARM: dts: tegra20: Add interrupt to External Memory Controller
>   clk: tegra20: Turn EMC clock gate into divider
>   clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
>   memory: tegra: Introduce Tegra20 EMC driver
> 

Series Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>