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[209.132.180.67]) by mx.google.com with ESMTP id f9-v6si5666561pgo.593.2018.06.05.08.37.56; Tue, 05 Jun 2018 08:38:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Yw1bAo0+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752241AbeFEPhZ (ORCPT + 99 others); Tue, 5 Jun 2018 11:37:25 -0400 Received: from mail-qt0-f196.google.com ([209.85.216.196]:38917 "EHLO mail-qt0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751747AbeFEPhX (ORCPT ); Tue, 5 Jun 2018 11:37:23 -0400 Received: by mail-qt0-f196.google.com with SMTP id p23-v6so2869241qtn.6; Tue, 05 Jun 2018 08:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dwscPLJDfLuNMxo6y7F2eU7f8zxVQjwt7KDF7YRtcPM=; b=Yw1bAo0+M7vqHYyLp0TnhLNiXuNdb7QDYwHnSC5WAe6rwJSVDhPjbfQ+6kIEWQPXT+ lMie+7YGudoi1+FQN3OaL4TAx+9NNVCpPVd2W0k24ANIcJeNpxYWfyu5J/9chXw//oV9 02xCFLV+vAqV2SD7QNxmP4lOuSPylCyNc+L2/uLQA7IGX8isVodEz0LlRHM5CaImwymL paAcwjLYrwMeWiTLstu54Y9ZRVztYt9q3q6/+Oc3Dh8kpsY9qHQ1LoYp/So2HjIbd8bq 8edd2/6NeC10KgBvO22RhgHjdZqaGtU1nVxwqfz5yaw60W66xRiqaQYoOWwSrR/Ke6RM ofag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dwscPLJDfLuNMxo6y7F2eU7f8zxVQjwt7KDF7YRtcPM=; b=t1MbFylXvPCLm2rzupsr94ro/At+CFWaiUUuFQGkbuOgREa4JrHvvxP9OBoyEp81Fd 2m3RxP4EJd39p55H69SMRUEVS+paHkmLCoCvIjKGorycjkAUnVHOZU5OMo9uh0yetzAT 04YN83qSvHe0HDGavTSUQDX7aQsiPEPwNgU7sMpLSHlbbDuT4fIqK8KL+NS9fhBtkMWk mi0yuWqp6yDKMs5LbldvSEzTSwvH+fxTkqwh4Xpzc0EXgZxA7QcI0PN2mor55PzzD28n 9QUwK1fiMBLQkN2fFwKTqJHzhG/ucbHDhNkpFW4kojYyvRQPTyzQh96w8u/PRYPIsIWC uh2g== X-Gm-Message-State: APt69E2xD9nKaA6ptrt0R44BUaozR6x1rFWTUtig30TFCJgpsOuYe64k XfvYsRKT8wwJDUQkOLfdBH7Qns7TQgGsrqM+fsXKECTt X-Received: by 2002:aed:3966:: with SMTP id l93-v6mr8878868qte.220.1528213042231; Tue, 05 Jun 2018 08:37:22 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a0c:98f9:0:0:0:0:0 with HTTP; Tue, 5 Jun 2018 08:37:21 -0700 (PDT) In-Reply-To: <20180523140635.GB27215@amd> References: <20180523140635.GB27215@amd> From: Andy Shevchenko Date: Tue, 5 Jun 2018 18:37:21 +0300 Message-ID: Subject: Re: [PATCH v7 3/3] gpio: pca953x: fix address calculation for pcal6524 To: Pavel Machek Cc: "H. Nikolaus Schaller" , Kumar Gala , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Linus Walleij , Alexandre Courbot , devicetree , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Discussions about the Letux Kernel , kernel@pyra-handheld.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 23, 2018 at 5:06 PM, Pavel Machek wrote: > On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: >> The register constants are so far defined in a way that they fit >> for the pcal9555a when shifted by the number of banks, i.e. are >> multiplied by 2 in the accessor function. >> >> Now, the pcal6524 has 3 banks which means the relative offset >> is multiplied by 4 for the standard registers. >> >> Simply applying the bit shift to the extended registers gives >> a wrong result, since the base offset is already included in >> the offset. >> >> Therefore, we have to add code to the 24 bit accessor functions >> that adjusts the register number for these exended registers. >> >> The formula finally used was developed and proposed by >> Andy Shevchenko . >> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); >> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; >> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; > Is this reasonable to do on each register access? Compiler will not be > able to optimize out fls and shifts, right? On modern CPUs fls() is one assembly command. OTOH, any proposal to do this better? What I can see is that bank_shift is invariant to the function, and maybe cached. -- With Best Regards, Andy Shevchenko