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Date:   Tue, 5 Jun 2018 22:39:41 +0200
From:   Pavel Machek <pavel@ucw.cz>
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
Cc:     "H. Nikolaus Schaller" <hns@goldelico.com>,
        Kumar Gala <galak@codeaurora.org>,
        Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Linus Walleij <linus.walleij@linaro.org>,
        Alexandre Courbot <gnurou@gmail.com>,
        devicetree <devicetree@vger.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Discussions about the Letux Kernel 
        <letux-kernel@openphoenux.org>, kernel@pyra-handheld.com
Subject: Re: [PATCH v7 3/3] gpio: pca953x: fix address calculation for
 pcal6524
Message-ID: <20180605203941.GA28143@amd>
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 <e70e83f07aebaf702fef90a9fac61e41d8b558b0.1526533188.git.hns@goldelico.com>
 <20180523140635.GB27215@amd>
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On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote:
> On Wed, May 23, 2018 at 5:06 PM, Pavel Machek <pavel@ucw.cz> wrote:
> > On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote:
> >> The register constants are so far defined in a way that they fit
> >> for the pcal9555a when shifted by the number of banks, i.e. are
> >> multiplied by 2 in the accessor function.
> >>
> >> Now, the pcal6524 has 3 banks which means the relative offset
> >> is multiplied by 4 for the standard registers.
> >>
> >> Simply applying the bit shift to the extended registers gives
> >> a wrong result, since the base offset is already included in
> >> the offset.
> >>
> >> Therefore, we have to add code to the 24 bit accessor functions
> >> that adjusts the register number for these exended registers.
> >>
> >> The formula finally used was developed and proposed by
> >> Andy Shevchenko <andy.shevchenko@gmail.com>.
>=20
> >>       int bank_shift =3D fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
> >> +     int addr =3D (reg & PCAL_GPIO_MASK) << bank_shift;
> >> +     int pinctrl =3D (reg & PCAL_PINCTRL_MASK) << 1;
>=20
> > Is this reasonable to do on each register access? Compiler will not be
> > able to optimize out fls and shifts, right?
>=20
> On modern CPUs fls() is one assembly command. OTOH, any proposal to do
> this better?
>=20
> What I can see is that bank_shift is invariant to the function, and
> maybe cached.

Yes, I thought that caching bank_shift might be good idea. I thought
it was constant for given chip...

Best regards,
									Pavel
--=20
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blo=
g.html

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