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Date:   Thu, 7 Jun 2018 17:12:37 +0300
From:   Alexander Shishkin <alexander.shishkin@linux.intel.com>
To:     Luwei Kang <luwei.kang@intel.com>
Cc:     kvm@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com,
        hpa@zytor.com, x86@kernel.org, chao.p.peng@linux.intel.com,
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        linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com,
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Subject: Re: [PATCH v9 10/12] KVM: x86: Implement Intel Processor Trace MSRs
 read/write emulation
Message-ID: <20180607141237.ruhg44wuepkf4nhz@um.fi.intel.com>
References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com>
 <1526964735-16566-11-git-send-email-luwei.kang@intel.com>
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On Tue, May 22, 2018 at 12:52:13PM +0800, Luwei Kang wrote:
> +	/*
> +	 * Any MSR write that attempts to change bits marked reserved will
> +	 * case a #GP fault.
> +	 */
> +	if (data & vmx->pt_desc.ctl_bitmask)
> +		return 1;
> +
> +	/*
> +	 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
> +	 * result in a #GP unless the same write also clears TraceEn.
> +	 */
> +	if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
> +		((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
> +		return 1;
> +
> +	/*
> +	 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
> +	 * and FabricEn would cause #GP, if
> +	 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
> +	 */
> +	if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
> +		!(data & RTIT_CTL_FABRIC_EN) &&
> +		!pt_cap_decode(vmx->pt_desc.caps, PT_CAP_single_range_output))
> +		return 1;

Ah, I see. But afaict this is still wrong: PT_CAP_single_range_output is
only about allowing !RTIT_CTL_TOPA, FABRIC_EN should be checked separately
against the new capability that you added in 4/12.

Regards,
--
Alex