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[209.132.180.67]) by mx.google.com with ESMTP id o26-v6si15290617pge.307.2018.06.08.07.26.47; Fri, 08 Jun 2018 07:27:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752716AbeFHO0O convert rfc822-to-8bit (ORCPT + 99 others); Fri, 8 Jun 2018 10:26:14 -0400 Received: from mga12.intel.com ([192.55.52.136]:15738 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752459AbeFHO0M (ORCPT ); Fri, 8 Jun 2018 10:26:12 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jun 2018 07:26:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,490,1520924400"; d="scan'208";a="235528157" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga005.fm.intel.com with ESMTP; 08 Jun 2018 07:26:11 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 8 Jun 2018 07:26:11 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.82]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.51]) with mapi id 14.03.0319.002; Fri, 8 Jun 2018 22:26:10 +0800 From: "Kang, Luwei" To: Alexander Shishkin CC: "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "chao.p.peng@linux.intel.com" , "thomas.lendacky@amd.com" , "bp@suse.de" , "Liang, Kan" , "Janakarajan.Natarajan@amd.com" , "dwmw@amazon.co.uk" , "linux-kernel@vger.kernel.org" , "peterz@infradead.org" , "mathieu.poirier@linaro.org" , "kstewart@linuxfoundation.org" , "gregkh@linuxfoundation.org" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "david@redhat.com" , "bsd@redhat.com" , "yu.c.zhang@linux.intel.com" , "joro@8bytes.org" Subject: RE: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Thread-Topic: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Thread-Index: AQHT8Xi40DWVm7BbrE+rqN9Qj2UB8qRUXxQAgAImVjA= Date: Fri, 8 Jun 2018 14:26:08 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FEFFF6@SHSMSX101.ccr.corp.intel.com> References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com> <1526964735-16566-4-git-send-email-luwei.kang@intel.com> <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> In-Reply-To: <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > These bit definitions are use for emulate MSRs read/write for KVM. For > > example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when > > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this > > bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected > > to KVM guest. > > Do we have anything in the guest that this feature will work with? > It depend on PT driver. KVM need to do some security check if kvm guest (maybe linux or other os) try to set any bits of these MSRs. Thanks, Luwei Kang