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From:   "Kang, Luwei" <luwei.kang@intel.com>
To:     Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Subject: RE: [PATCH v9 04/12] perf/x86/intel/pt: add new capability for
 Intel PT
Thread-Topic: [PATCH v9 04/12] perf/x86/intel/pt: add new capability for
 Intel PT
Thread-Index: AQHT8Xi9oYPMthILhkSzx/04cBEj8qRUYT6AgAIliWA=
Date:   Fri, 8 Jun 2018 14:34:53 +0000
Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FF006E@SHSMSX101.ccr.corp.intel.com>
References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com>
 <1526964735-16566-5-git-send-email-luwei.kang@intel.com>
 <20180607134051.rwu5pqtz45cgq7ve@um.fi.intel.com>
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> > CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1 indicates support of output to
> > Trace Transport subsystem.
> > MSR IA32_RTIT_CTL.FabricEn[bit 6] is reserved if CPUID.(EAX=14H,
> > ECX=0):ECX[bit 3] = 0.
> 
> This should instead say:
> 
> This adds support for "output to Trace Transport subsystem" capability of
> Intel PT, as documented in IA SDM Chapter 36.x.y.z. It means that PT can
> output its trace to an MMIO address range rather than system memory
> buffer.

Yes, you are right. In KVM point of view this bit use for MSR access security check.
KVM will track MSRs access in guest, an #GP will be injected to guest if guest try to write IA32_RTIT_CTL.FabricEn[bit 6]  when "output_subsys" (CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0) is not supported.

Thanks,
Luwei Kang

> 
> > This is use for emulate IA32_RTIT_CTL MSR read/write in KVM. KVM guest
> > write IA32_RTIT_CTL will trap to root mode and a #GP would be injected
> > to guest if set IA32_RTIT_CTL.FabricEn with CPUID.(EAX=14H,
> > ECX=0):ECX[bit 3] = 0.
> 
> I'm not sure what this means, this patch has nothing to do with KVM as far as
> I can tell.
> 
> Aside from the commit message, this is a valid patch.
> 
> Thanks,
> --
> Alex