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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id w102-v6sm496182wrc.23.2018.06.12.07.50.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 07:50:09 -0700 (PDT) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, david.brown@linaro.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH] arm64: dts: apq8096-db820c: disable uart0 by default Date: Tue, 12 Jun 2018 15:48:06 +0100 Message-Id: <20180612144806.19201-1-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.16.2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Access to UART0 is disabled by bootloaders. By leaving it enabled by default would reboot the board. Disable this for now, this would alteast give a board which boots. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 0f829db33efe..4d5ef01f43a3 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -75,7 +75,7 @@ serial@75b1000 { label = "LS-UART0"; - status = "okay"; + status = "disabled"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_uart2_4pins_default>; pinctrl-1 = <&blsp2_uart2_4pins_sleep>; -- 2.16.2