Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S261761AbTIFXKL (ORCPT ); Sat, 6 Sep 2003 19:10:11 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S261826AbTIFXKL (ORCPT ); Sat, 6 Sep 2003 19:10:11 -0400 Received: from mail.jlokier.co.uk ([81.29.64.88]:25742 "EHLO mail.jlokier.co.uk") by vger.kernel.org with ESMTP id S261761AbTIFXKI (ORCPT ); Sat, 6 Sep 2003 19:10:08 -0400 Date: Sun, 7 Sep 2003 00:09:12 +0100 From: Jamie Lokier To: Pavel Machek Cc: Alan Cox , nagendra_tomar@adaptec.com, Geert Uytterhoeven , Roman Zippel , Kars de Jong , Linux/m68k kernel mailing list , Linux Kernel Development Subject: Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this Message-ID: <20030906230911.GA12392@mail.jlokier.co.uk> References: <1062674382.21667.32.camel@dhcp23.swansea.linux.org.uk> <20030905212420.GD220@elf.ucw.cz> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20030905212420.GD220@elf.ucw.cz> User-Agent: Mutt/1.4.1i Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 754 Lines: 19 Pavel Machek wrote: > > x86 gives you coherency and store ordering (barring errata and special > > CPU modes) > > Special CPU modes? You mean some special SSE stores? Take a look at arch/i386/kernel/cpu/centaur.c, and CONFIG_X86_OOSTORE. You can change the memory settings to weakly ordered writes, which means that a plain write isn't suitable for spin_unlock. Presumably this mode is faster (though I don't see why, if Intel, AMD et al. can manage good memory performance without weak writes). -- Jamie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/