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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id k84-v6sm1517478pfh.110.2018.06.12.12.26.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 12:26:38 -0700 (PDT) Date: Tue, 12 Jun 2018 13:26:36 -0600 From: Rob Herring To: Sayali Lokhande Cc: subhashj@codeaurora.org, cang@codeaurora.org, vivek.gautam@codeaurora.org, rnayak@codeaurora.org, vinholikatti@gmail.com, jejb@linux.vnet.ibm.com, martin.petersen@oracle.com, asutoshd@codeaurora.org, evgreen@chromium.org, linux-scsi@vger.kernel.org, Mark Rutland , Mathieu Malaterre , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH V2 1/3] scsi: ufs: set the device reference clock setting Message-ID: <20180612192636.GA31725@rob-hp-laptop> References: <1528455990-24572-1-git-send-email-sayalil@codeaurora.org> <1528455990-24572-2-git-send-email-sayalil@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1528455990-24572-2-git-send-email-sayalil@codeaurora.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 08, 2018 at 04:36:28PM +0530, Sayali Lokhande wrote: > From: Subhash Jadavani > > UFS host supplies the reference clock to UFS device and UFS device > specification allows host to provide one of the 4 frequencies (19.2 MHz, > 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the > device reference clock frequency setting in the device based on what > frequency it is supplying to UFS device. > > Signed-off-by: Subhash Jadavani > Signed-off-by: Can Guo > Signed-off-by: Sayali Lokhande > --- > .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 7 +++ > drivers/scsi/ufs/ufs.h | 9 ++++ > drivers/scsi/ufs/ufshcd-pltfrm.c | 24 ++++++++++ > drivers/scsi/ufs/ufshcd.c | 52 ++++++++++++++++++++++ > drivers/scsi/ufs/ufshcd.h | 1 + > 5 files changed, 93 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt > index c39dfef..4522434 100644 > --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt > +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt > @@ -41,6 +41,12 @@ Optional properties: > -lanes-per-direction : number of lanes available per direction - either 1 or 2. > Note that it is assume same number of lanes is used both > directions at once. If not specified, default is 2 lanes per direction. > +- dev-ref-clk-freq : Specify the device reference clock frequency, must be one of the following: > + 0: 19.2 MHz > + 1: 26 MHz > + 2: 38.4 MHz > + 3: 52 MHz > + Defaults to 26 MHz if not specified. I must have misunderstood your last response. I thought you could handle things without DT. If not, my question remains. Rob