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[209.132.180.67]) by mx.google.com with ESMTP id e129-v6si2140869pfg.112.2018.06.13.00.18.13; Wed, 13 Jun 2018 00:18:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934669AbeFMHRo (ORCPT + 99 others); Wed, 13 Jun 2018 03:17:44 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:3750 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S933999AbeFMHRm (ORCPT ); Wed, 13 Jun 2018 03:17:42 -0400 X-UUID: d49583569ab64ff095868ea42a4feb27-20180613 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 939864625; Wed, 13 Jun 2018 15:17:36 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 13 Jun 2018 15:17:35 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 13 Jun 2018 15:17:35 +0800 Message-ID: <1528874255.30263.7.camel@mtksdaap41> Subject: Re: [PATCH 20/28] drm/mediatek: add connection from RDMA2 to DSI1 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Wed, 13 Jun 2018 15:17:35 +0800 In-Reply-To: <1528687580-549-21-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> <1528687580-549-21-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: On Mon, 2018-06-11 at 11:26 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA2 to DSI1 > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 2d883815d79c..ae10f8f1e140 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -94,11 +94,13 @@ > #define RDMA1_MOUT_DPI1 0x3 > #define RDMA2_MOUT_DPI0 0x2 > #define RDMA2_MOUT_DPI1 0x3 > +#define RDMA2_MOUT_DSI1 0x1 > #define DPI0_SEL_IN_RDMA1 0x1 > #define DPI0_SEL_IN_RDMA2 0x3 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > #define DPI1_SEL_IN_RDMA2 (0x3 << 8) > #define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > #define DSI3_SEL_IN_RDMA1 (0x1 << 16) > #define COLOR1_SEL_IN_OVL1 0x1 > @@ -198,6 +200,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; > value = RDMA1_MOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_MOUT_DSI1; > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > value = RDMA2_MOUT_DPI0; > @@ -241,6 +246,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > value = COLOR1_SEL_IN_OVL1;