Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp620820imm; Wed, 13 Jun 2018 05:59:20 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKm7yYYLilGmrIcj4K1/YX5atuX7prXVHOmpZFiHrGkqqk5KtIsni7VVppIRXZP8t0rDR9I X-Received: by 2002:a63:a042:: with SMTP id u2-v6mr4108074pgn.413.1528894760172; Wed, 13 Jun 2018 05:59:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894760; cv=none; d=google.com; s=arc-20160816; b=nIhoMpg4+5CVaFoKbM+wlc5JMwV6Zgatodljrh4MPHWq8RQyF/FbSzLq4wIVu7eQpN dc8qHYUgnszstRJ6dp7574vSRIbDvIVGYHUZjSa4AZgBaE8t7PUzHJehYkQrPyHTEz/9 gZ/Puz7sHmeSls2N2xfsgXmIuKJy7yVo+B2n1x2RjiUyW4moexD6jQZkXqzOB4up2yO0 zgyfBzyDsqDX3HUoYOFEHytB2hSyfyCCeTkxA6cgb1V3Jg6N1ariNhBHLnoCgtEFFXjr dYXvonziYBFQJ4VgUsBf/cs/P475kEmQOMfA6BK9w9+VniqI+Hq8cilUMw9kuZ/ZEHIC sAIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=mxedaqgD1/fKXxLiU9zTEqZXgzsnv95tmxSJvY2PBIk=; b=qSz/2Fo28KBo6mW9JOB+pt/TUZqes+STYcwRA9bvFxgkgEG//DJKytuTdY28g22KdC W1HVyPmmDxbjvnsYHeJ9IN9Un+FFoW95jq0wKkKeeWbE/epkkPRoZJl3AhhXscWh1hJv Whg1Ssqk80ZmCzUH7ongPcN/Fr9P/l0brbaAdRv/6Uq7ExfYGck6o65qJGJ2UDYa5tvJ ZYwfJ8nhxqQy5UHXHsYxa3wrApnjYEPPHPx2KRf0jB2gYXDNB8rhmS7FxXhjw8uqTCxX 5LN2OMqnsu4LWr16Nr2Jz5WfaBF0P1JJIxN5s/bXYG8FLM9iS2AqkPNaxYl+MCOfU24Z 1Qrw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b83-v6si2980843pfk.342.2018.06.13.05.59.05; Wed, 13 Jun 2018 05:59:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935704AbeFMM45 convert rfc822-to-8bit (ORCPT + 99 others); Wed, 13 Jun 2018 08:56:57 -0400 Received: from gloria.sntech.de ([95.129.55.99]:41764 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935570AbeFMM4y (ORCPT ); Wed, 13 Jun 2018 08:56:54 -0400 Received: from ip9234b215.dynamic.kabel-deutschland.de ([146.52.178.21] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fT5KO-00078J-J0; Wed, 13 Jun 2018 14:56:44 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: klaus.goger@theobroma-systems.com Cc: Randy Li , linux-rockchip@lists.infradead.org, Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Catalin Marinas , Will Deacon , LKML , Rob Herring , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Shawn Lin Subject: Re: [PATCH] ARM64: dts: rockchip: add some pins to rk3399 Date: Wed, 13 Jun 2018 14:56:43 +0200 Message-ID: <6575089.GrJ2ErpgXD@diego> In-Reply-To: References: <20180612152544.3812-1-ayaka@soulik.info> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 12. Juni 2018, 20:21:06 CEST schrieb klaus.goger@theobroma- systems.com: > Hi Randy, > > > On 12.06.2018, at 17:25, Randy Li wrote: > > > > Those pins would be used by many boards. > > > > Signed-off-by: Randy Li agree to everything Klaus said ;-) . [...] > > + pcie_clkreqn: pci-clkreqn { > > + rockchip,pins = > > + <2 26 RK_FUNC_2 &pcfg_pull_none>; > > + }; > > + > > + pcie_clkreqnb: pci-clkreqnb { > > + rockchip,pins = > > + <4 24 RK_FUNC_1 &pcfg_pull_none>; > > + }; > > + > > I’m not sure if pci-clkreqn is functional at all. If not I’m not sure if we > should add it to the dtsi. Shawn may know more about it. Yep, wasn't there a big change away from clkreqn, due it not being functional? > > pcie_clkreqnb_cpm: pci-clkreqnb-cpm { > > > > rockchip,pins = > > > > - <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; > > + <4 24 RK_FUNC_GPIO &pcfg_pull_none>; > > > > }; > > > > }; > > Could we actually use RK_Pxx for all new pin definitions? Would increase > readability a lot. Especially as the above change really only seems to change RK_PD0 back to 24, so this block (and some others) will go away entirely. Heiko