Message-ID: <3F5B96C3.1060706@colorfullife.com>
Date: Sun, 07 Sep 2003 22:36:19 +0200
From: Manfred Spraul <manfred@colorfullife.com>
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To: Adrian Bunk <bunk@fs.tum.de>
CC: linux-kernel@vger.kernel.org, peter_daum@t-online.de
Subject: Re: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT
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Adrian wrote:

>With CONFIG_M686 CONFIG_X86_L1_CACHE_SHIFT was set to 5, but a Pentium 4 
>requires 7.
>  
>
Why requires? On x86, the cpu caches are fully coherent. A too small L1 
cache shift results in false sharing on SMP, but it shouldn't cause the 
described problems.

And obviously: Pentium II cpus have a 32 byte cache line, increasing the 
L1 setting to 128 bytes only helps by chance.

My bet is that someone overwrites critical memory structures, and with 
more padding, the critical stuff is further away.

--
    Manfred


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