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[209.132.180.67]) by mx.google.com with ESMTP id k185-v6si4310156pgd.22.2018.06.14.04.49.29; Thu, 14 Jun 2018 04:49:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755126AbeFNLsC (ORCPT + 99 others); Thu, 14 Jun 2018 07:48:02 -0400 Received: from esa5.microchip.iphmx.com ([216.71.150.166]:61922 "EHLO esa5.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755084AbeFNLsA (ORCPT ); Thu, 14 Jun 2018 07:48:00 -0400 X-IronPort-AV: E=Sophos;i="5.51,222,1526367600"; d="scan'208";a="13058429" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 14 Jun 2018 04:47:55 -0700 Received: from [10.159.245.112] (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.352.0; Thu, 14 Jun 2018 04:47:53 -0700 Subject: Re: [PATCH 2/4] arm: dts: add support for Laird WB50N cpu module and DVK To: Alexandre Belloni , Ben Whitten CC: , Ben Whitten , "Rob Herring" , Mark Rutland , , References: <1528966340-23216-1-git-send-email-ben.whitten@lairdtech.com> <1528966340-23216-2-git-send-email-ben.whitten@lairdtech.com> <20180614095041.GW10521@piout.net> From: Nicolas Ferre Organization: microchip Message-ID: <6f434031-19b9-bd3f-1e9f-e1b862a50d40@microchip.com> Date: Thu, 14 Jun 2018 13:47:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180614095041.GW10521@piout.net> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/06/2018 at 11:50, Alexandre Belloni wrote: > On 14/06/2018 09:51:55+0100, Ben Whitten wrote: >> Signed-off-by: Ben Whitten >> --- >> arch/arm/boot/dts/Makefile | 3 +- >> arch/arm/boot/dts/at91-wb50n.dts | 116 ++++++++++++++++++++++ >> arch/arm/boot/dts/at91-wb50n.dtsi | 202 ++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 320 insertions(+), 1 deletion(-) >> create mode 100644 arch/arm/boot/dts/at91-wb50n.dts >> create mode 100644 arch/arm/boot/dts/at91-wb50n.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 1ee94ee..fd5f8a6 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -61,7 +61,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ >> at91-sama5d4_ma5d4evk.dtb \ >> at91-sama5d4_xplained.dtb \ >> at91-sama5d4ek.dtb \ >> - at91-vinco.dtb >> + at91-vinco.dtb \ >> + at91-wb50n.dtb > > I know we have been bad at this but this should be > at91--.dtb so at91-sama5d31-wb50n.dtb See new message by Alexandre. Actually, the current convention is explained here: https://elixir.bootlin.com/linux/latest/source/Documentation/arm/Microchip/README#L159 >> dtb-$(CONFIG_ARCH_ATLAS6) += \ >> atlas6-evb.dtb >> dtb-$(CONFIG_ARCH_ATLAS7) += \ >> diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts >> new file mode 100644 >> index 0000000..ee4f823 >> --- /dev/null >> +++ b/arch/arm/boot/dts/at91-wb50n.dts >> @@ -0,0 +1,116 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * at91-wb50n.dts - Device Tree file for wb50n evaluation board >> + * >> + * Copyright (C) 2018 Laird >> + * >> + */ >> + >> +/dts-v1/; >> +#include "at91-wb50n.dtsi" >> + >> +/ { >> + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; >> + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; >> + >> + ahb { >> + apb { >> + watchdog@fffffe40 { > > I don't mind if you want to have a preparation patch adding the > necessary labels in the soc dtsi so you don't have to reproduce the > ahb/apb hierarchy here. I agree: +1 >> + ahb { >> + apb { >> + pinctrl@fffff200 { > > Ditto > >> + board { >> + pinctrl_mmc0_cd: mmc0_cd { >> + atmel,pins = ; /* PC26 GPIO with pullup deglitch */ >> + }; >> + >> + pinctrl_usba_vbus: usba_vbus { >> + atmel,pins = ; /* PB13 GPIO with deglitch */ >> + }; >> + }; >> + }; >> + }; >> + }; >> +}; >> + >> +&slow_osc { >> + atmel,osc-bypass; >> +}; > > After the clock binding rework, this will have to be moved to the pmc > node (the rework is not posted, this is just to remind me that this will > have to be done). > >> + >> +&usart1_clk { >> + atmel,clk-output-range = <0 132000000>; >> +}; > > The datasheet explicitly states that 66 MHz is the maximum allowed > frequency for the USART. Note that the new binding will not allow you to > do that. > > However, I see the table disappeared from the latest datasheet. Maybe > Nicolas can comment on that? You're right, 66 MHz is the maximum frequency for all USART and UART on this sama5d3 SoC. The disappearing of this table is a bug in the latest datasheet. I can see that the one "11121B–ATARM–08-Mar-13" still have it. I report this issue to the team in charge of datasheets (it will be certainly fixed for next release of this document). Best regards, -- Nicolas Ferre