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McKenney" , Ralf Baechle Message-ID: <1373980460.14412.1529084239034.JavaMail.zimbra@efficios.com> In-Reply-To: <20180615105809.GB7603@jamesdev> References: <20180614235211.31357-1-paul.burton@mips.com> <20180614235211.31357-5-paul.burton@mips.com> <20180615105809.GB7603@jamesdev> Subject: Re: [PATCH 4/4] rseq/selftests: Implement MIPS support MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Originating-IP: [167.114.142.138] X-Mailer: Zimbra 8.8.8_GA_2096 (ZimbraWebClient - FF52 (Linux)/8.8.8_GA_1703) Thread-Topic: rseq/selftests: Implement MIPS support Thread-Index: sJDkoLXztL0rd01o4PFqQYpfV3YGlA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ----- On Jun 15, 2018, at 6:58 AM, James Hogan jhogan@kernel.org wrote: > On Thu, Jun 14, 2018 at 04:52:10PM -0700, Paul Burton wrote: >> +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip, \ > > Nit: technically all these \'s are on 81st column... > >> +#define __RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, \ >> + abort_label, version, flags, \ >> + start_ip, post_commit_offset, abort_ip) \ >> + ".balign 32\n\t" \ > > ARM doesn't do this for DEFINE_ABORT. Is it intentional that we do for > MIPS? Given that include/uapi/linux/rseq.h declares struct rseq_cs as __attribute__((aligned(4 * sizeof(__u64)))), and considering this comment: /* * struct rseq_cs is aligned on 4 * 8 bytes to ensure it is always * contained within a single cache-line. It is usually declared as * link-time constant data. */ The .balign 32 is the right thing to do here. I will add a .balign 32 to ARM selftests code as well. Thanks, Mathieu > > Thanks > James -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com