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[209.132.180.67]) by mx.google.com with ESMTP id g12-v6si14182526pla.194.2018.06.18.01.58.56; Mon, 18 Jun 2018 01:59:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967746AbeFRI5c (ORCPT + 99 others); Mon, 18 Jun 2018 04:57:32 -0400 Received: from mail-ua0-f196.google.com ([209.85.217.196]:37988 "EHLO mail-ua0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967699AbeFRI5a (ORCPT ); Mon, 18 Jun 2018 04:57:30 -0400 Received: by mail-ua0-f196.google.com with SMTP id 59-v6so10204985uas.5; Mon, 18 Jun 2018 01:57:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IaEh0sYT5va1hWQr05QQ7KHhPEs4HDtHWNGL8rX7y3Q=; b=McbKNNyhqhuIFmG6jkLzWdEDO6UDwWj3cEuekSmcLkysB/5ctbBik0r+ikLZH2gJDU PST0M+R28+LgKsfhVS0tSJh5128hMweI0eLu38KLLrL07pVrLroZI7ztKHsEJMEWBN/C VUK8elyECsSSILS4AItEFECrJ/ZX56jJsrpanuMyeVxsdZdjiYNHksZzRDSFyZt7Fk17 CMlEFk+QvtP8tk8WL1FjeJwQDoo9q2U2UPJQm2du4RHKEscpylgwWIXGM1gYv2QIu/r0 xmvHtvNZqzA7raG0jibe6nHSP26RdAXTphyg0XJOqarIfsglgEABXx9VTe33tmK6eerL w9Ow== X-Gm-Message-State: APt69E3FK2XxB49bPWmdqaGjgKQo2EEmvN/n6LhatmGW23Ab1vEv/Jm8 nMUISYwc1rCEQJ7muPLkB8LiODaMs/6L5AqZka4= X-Received: by 2002:ab0:5b18:: with SMTP id u24-v6mr7240782uae.72.1529312249528; Mon, 18 Jun 2018 01:57:29 -0700 (PDT) MIME-Version: 1.0 References: <1528974029-29617-1-git-send-email-michel.pollet@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 18 Jun 2018 10:57:18 +0200 Message-ID: Subject: Re: [PATCH v1 0/5] Renesas R9A06G032 PINCTRL Driver To: Linus Walleij Cc: Michel Pollet , Geert Uytterhoeven , Laurent Pinchart , Linux-Renesas , Simon Horman , Phil Edworthy , Michel Pollet , Rob Herring , Mark Rutland , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Magnus Damm Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, On Mon, Jun 18, 2018 at 10:46 AM Linus Walleij wrote: > On Thu, Jun 14, 2018 at 1:00 PM, Michel Pollet > wrote: > > > *WARNING* -- this requires: > > + R9A06G032 base patch v9 > > + R9A06G032 SMP patch v5 > > Is that required for the pin controller itself (compile-time dependence) > or is it required to boot the system (run-time dependence)? Obviously the last 3 patches in the series touch the DTS, so they depend on the base patch adding the DTS files. > We can merge support for pin control ahead, that's fine. The actual pinctrl driver can indeed be merged separately. > > This implements the pinctrl driver for the R9A06G032. > > Geert Uytterhoeven and Laurent Pinchart maintains the Renesas pin > controllers, and this one is for some reason a totally new one in > drivers/pinctrl/pinctrl-r9a06g032.c > > Is it totally different from the other "great old ones" in the SuperH-PFC > series or is there some other reason why it was done like this? Yes it is, cfr. drivers/pinctrl/pinctrl-rza1.c, which lives outside sh-pfc, too. Of course I can take it through my sh-pfc tree, once the rough edges have been removed. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds