Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp3691779imm; Mon, 18 Jun 2018 02:23:28 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKugsoaTMuhj/HL2Jo5qrdSCCbvcsK3qk/xngDVNzqUFFAr7Z9Vt3JxXG7QwX+8Ead4bJsN X-Received: by 2002:a17:902:6acc:: with SMTP id i12-v6mr13212678plt.278.1529313808229; Mon, 18 Jun 2018 02:23:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529313808; cv=none; d=google.com; s=arc-20160816; b=f9Ke84X+SAs6HZpKE5Ju/ti5ZRT0St4J4/K+i5zlttg2WzrDcOQHTtb7fSZVjDj3XI wquGtUptf3JjH45kNrc7ClTF/sOShaCa086mu4PVkDCOj6NYPH7p7rIKrMvS9Xm8i/Tz 6lbCJSwcQXpSPTdgROW38NqGSFb3ZMqVpC8x++jvmQCPV+Nt0Dvh0VN1eU4aIFeAIvnh +/6Hd3NkEgSOW4l++G+oSdm0h8/P9cdq1tL6AzAXHPvqqMyFlI7uZqUCno7v/rnQIdKg cfaLlccndZiid7iqOg6hCyuQJ+J22N3E0Ozr28yfIJ8qg2dt2f7igcpx9g9j0hYhK/RG aOxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:user-agent:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=PwlQ3mtKVCTMpyHu4M9gF9qvvtl6UMSCIbuctW/exH0=; b=QoGGwEr8yuMm1uO3s+yabZjQPE5LFm201a5PIdesFwHt5NVwdc89qwT/VZB6Yr5Ubj AiJ4Fk0d1KFX47aaYaLBzaNxqxFnCKuMh92AyJB231PazTI1mzFrAFTiVbHCooiwT0I/ 8XPIJfJzx1KqxZ2q6yJsF8dG5WLMoT7k5VBK6gqVcg4FGx7foJUQb07GOMcNVVMf8Tmx gWIrPEKxwTPj2XePSSNjxxxwwlY0XhVeUjeL8msF66lQVcakIdk9jId5O2bJh9Ufq8RM lOwQ3pDwKJ9vqSD3XG5tzArpmgVJ73yzdDin+AMNEey+2HxWfiCAfBky7RKUfeMr/aXK epQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e90-v6si13989187pfb.185.2018.06.18.02.23.14; Mon, 18 Jun 2018 02:23:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966482AbeFRI1k (ORCPT + 99 others); Mon, 18 Jun 2018 04:27:40 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:57978 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965883AbeFRI1h (ORCPT ); Mon, 18 Jun 2018 04:27:37 -0400 Received: from localhost (LFbn-1-12247-202.w90-92.abo.wanadoo.fr [90.92.61.202]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 3176CCA8; Mon, 18 Jun 2018 08:27:36 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Sekhar Nori , Sasha Levin Subject: [PATCH 4.16 261/279] ARM: davinci: dm646x: fix timer interrupt generation Date: Mon, 18 Jun 2018 10:14:06 +0200 Message-Id: <20180618080619.516461584@linuxfoundation.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618080608.851973560@linuxfoundation.org> References: <20180618080608.851973560@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.16-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sekhar Nori [ Upstream commit 73d4337ed9ceddef4b2f0e226634d5f985aa2d1c ] commit b38434145b34 ("ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x") inadvertently removed priority setting for timer0_12 (bottom half of timer0). This timer is used as clockevent. When INTPRIn register setting for an interrupt is left at 0, it is mapped to FIQ by the AINTC causing the timer interrupt to not get generated. Fix it by including an entry for timer0_12 in interrupt priority map array. While at it, move the clockevent comment to the right place. Fixes: b38434145b34 ("ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x") Signed-off-by: Sekhar Nori Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-davinci/dm646x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -495,7 +495,8 @@ static u8 dm646x_default_priorities[DAVI [IRQ_DM646X_MCASP0TXINT] = 7, [IRQ_DM646X_MCASP0RXINT] = 7, [IRQ_DM646X_RESERVED_3] = 7, - [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ + [IRQ_DM646X_MCASP1TXINT] = 7, + [IRQ_TINT0_TINT12] = 7, /* clockevent */ [IRQ_TINT0_TINT34] = 7, /* clocksource */ [IRQ_TINT1_TINT12] = 7, /* DSP timer */ [IRQ_TINT1_TINT34] = 7, /* system tick */