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[209.132.180.67]) by mx.google.com with ESMTP id o33-v6si14532439pld.170.2018.06.18.03.06.48; Mon, 18 Jun 2018 03:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935340AbeFRKFf (ORCPT + 99 others); Mon, 18 Jun 2018 06:05:35 -0400 Received: from mga06.intel.com ([134.134.136.31]:33469 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934927AbeFRKFU (ORCPT ); Mon, 18 Jun 2018 06:05:20 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jun 2018 03:05:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,238,1526367600"; d="scan'208";a="58164420" Received: from zhuyixin-mobl1.gar.corp.intel.com (HELO [10.226.38.83]) ([10.226.38.83]) by FMSMGA003.fm.intel.com with ESMTP; 18 Jun 2018 03:05:16 -0700 Subject: Re: [PATCH 2/7] clk: intel: Add clock driver for GRX500 SoC To: Rob Herring Cc: Songjun Wu , hua.ma@linux.intel.com, chuanhua.lei@linux.intel.com, Linux-MIPS , qi-ming.wu@intel.com, linux-clk , "open list:SERIAL DRIVERS" , devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , "linux-kernel@vger.kernel.org" , Mark Rutland References: <20180612054034.4969-1-songjun.wu@linux.intel.com> <20180612054034.4969-3-songjun.wu@linux.intel.com> <20180612223725.GC2197@rob-hp-laptop> <41163f48-ce5c-efae-2b6d-b93d75e422e5@linux.intel.com> From: yixin zhu Message-ID: <4bb8f16e-2663-3a62-3c09-dc58fcb11831@linux.intel.com> Date: Mon, 18 Jun 2018 18:05:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/14/2018 10:09 PM, Rob Herring wrote: > On Thu, Jun 14, 2018 at 2:40 AM, yixin zhu wrote: >> >> >> On 6/13/2018 6:37 AM, Rob Herring wrote: >>> >>> On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote: >>>> >>>> From: Yixin Zhu >>>> >>>> PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below > > [...] > >>>> +Example: >>>> + clkgate0: clkgate0 { >>>> + #clock-cells = <1>; >>>> + compatible = "intel,grx500-gate0-clk"; >>>> + reg = <0x114>; >>>> + clock-output-names = "gate_xbar0", "gate_xbar1", >>>> "gate_xbar2", >>>> + "gate_xbar3", "gate_xbar6", "gate_xbar7"; >>>> + }; >>> >>> >>> We generally don't do a clock node per clock or few clocks but rather 1 >>> clock node per clock controller block. See any recent clock bindings. >>> >>> Rob >> >> Do you mean only one example is needed per clock controller block? >> cpuclk is not needed in the document? > > No, I mean generally we have 1 DT node for the h/w block with all the > clock control registers rather than nodes with a single register and 1 > or a couple of clocks. Sometimes the clock registers are mixed with > other functions which complicates things a bit. But I can't tell that > here because you haven't documented what's in the rest of the register > space. > > Rob > Thanks Will update to use one DT node for the whole clock controller.