Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp3731753imm; Mon, 18 Jun 2018 03:09:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIbJ7y5iKoJ92aQOzj75wP4sO9u5Yi1T8OrlPTvbte4vjggjuu671k90apQkgqQhSnSQQRe X-Received: by 2002:a62:3bd2:: with SMTP id w79-v6mr12879057pfj.129.1529316557023; Mon, 18 Jun 2018 03:09:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529316556; cv=none; d=google.com; s=arc-20160816; b=JcpO3FVPgI6VBgC/HxEjHE+woWlDgzXVgSPzk72L99Q704xtXGEm5DskvV8sPnWr9s Sxq4zX/0vUmnsBMcfeR2vgSfM0pcqR9YBw0Ru7rWE5tbybPQecNs3+VpawyD9vYGfUG9 2pFaSC3/eaxZKo2cZxW18CJRFlXlNqZjrapE31Lq71eMTQT6NDNmhChGb15ss5t9+cYw wNFdhW7Xr6WRi9ndgczBoAnwdF+yGzOhAn4097nMFDna1fCb+jxc2HPHn03uBO5Ypajh r4S9udaiCyY9hQdtwUsVQRKBIB3swJU9MFTjxEISsM3X1UrY8jVuB/ezXaEFnzDAiG1H jalA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=r2UQl3dP0DgAxDpzRW34M7qaIS/6rFYIio4c2CmGxZc=; b=dXt6xt622NwcE44onJRAiY2t7mBabdZ+bnBxRWRcZilIZNIbWHTKtC7OxWE5A0G/C+ eKwxAkVysDYD+ywMG11yIwirb1clTbueq2IllG+CBEG53vi4txlfvs1vQLb7xctRwh2R QcJXz0U/mys/y/qvZvVm3sfOK1baVMrZR9IcxqoPmNqgTHxiqn/2WtjAkjcPjOxe5NJ1 73sANLJ/noNz1e5A+KvFQPGd4Qd5O6W33eCN7rQhyQKxxc1p3QsP8ufVermbLaCSeIfu s6BR24FaXGHVJDm+6r2J0uMihGmKWBuoHI+1gsBtrqZfsgc4fS0g9cBYwyg6KO6ozP/H mqTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r9-v6si11700885pgf.664.2018.06.18.03.09.03; Mon, 18 Jun 2018 03:09:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936043AbeFRKHt (ORCPT + 99 others); Mon, 18 Jun 2018 06:07:49 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:36981 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934967AbeFRKHp (ORCPT ); Mon, 18 Jun 2018 06:07:45 -0400 X-IronPort-AV: E=Sophos;i="5.51,238,1526367600"; d="scan'208";a="15346660" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 18 Jun 2018 03:07:44 -0700 Received: from m19893.microchip.com (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.352.0; Mon, 18 Jun 2018 03:07:43 -0700 From: Radu Pirea To: , , , , , , , CC: , , , , , Radu Pirea Subject: [PATCH v8 2/6] dt-bindings: add binding for atmel-usart in SPI mode Date: Mon, 18 Jun 2018 13:08:25 +0300 Message-ID: <20180618100829.13875-3-radu.pirea@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180618100829.13875-1-radu.pirea@microchip.com> References: <20180618100829.13875-1-radu.pirea@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch moves the bindings for serial from serial/atmel-usart.txt to mfd/atmel-usart.txt and adds bindings for USART in SPI mode. Signed-off-by: Radu Pirea Reviewed-by: Rob Herring --- .../bindings/{serial => mfd}/atmel-usart.txt | 25 +++++++++++++++++-- include/dt-bindings/mfd/at91-usart.h | 17 +++++++++++++ 2 files changed, 40 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{serial => mfd}/atmel-usart.txt (76%) create mode 100644 include/dt-bindings/mfd/at91-usart.h diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt similarity index 76% rename from Documentation/devicetree/bindings/serial/atmel-usart.txt rename to Documentation/devicetree/bindings/mfd/atmel-usart.txt index 7c0d6b2f53e4..3b9e18642c3b 100644 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt @@ -1,6 +1,6 @@ * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) -Required properties: +Required properties for USART: - compatible: Should be "atmel,-usart" or "atmel,-dbgu" The compatible indicated will be the first SoC to support an additional mode or an USART new feature. @@ -11,7 +11,13 @@ Required properties: Required elements: "usart" - clocks: phandles to input clocks. -Optional properties: +Required properties for USART in SPI mode: +- #size-cells : Must be <0> +- #address-cells : Must be <1> +- cs-gpios: chipselects (internal cs not supported) +- atmel,usart-mode : Must be (found in dt-bindings/mfd/at91-usart.h) + +Optional properties in serial mode: - atmel,use-dma-rx: use of PDC or DMA for receiving data - atmel,use-dma-tx: use of PDC or DMA for transmitting data - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. @@ -62,3 +68,18 @@ Example: dma-names = "tx", "rx"; atmel,fifo-size = <32>; }; + +- SPI mode: + #include + + spi0: spi@f001c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; + atmel,usart-mode = ; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usart0_clk>; + clock-names = "usart"; + cs-gpios = <&pioB 3 0>; + }; diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h new file mode 100644 index 000000000000..2de5bc312e1e --- /dev/null +++ b/include/dt-bindings/mfd/at91-usart.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for AT91 USART DT bindings. + * + * Copyright (C) 2018 Microchip Technology + * + * Author: Radu Pirea + * + */ + +#ifndef __DT_BINDINGS_AT91_USART_H__ +#define __DT_BINDINGS_AT91_USART_H__ + +#define AT91_USART_MODE_SERIAL 0 +#define AT91_USART_MODE_SPI 1 + +#endif /* __DT_BINDINGS_AT91_USART_H__ */ -- 2.17.1