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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8b96215d-6f55-4a55-39a1-08d5d51fef61 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jun 2018 13:32:27.9153 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0402MB2760 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org -----Original Message----- From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]=20 Sent: Friday, June 15, 2018 7:26 PM To: Yogesh Narayan Gaur ; Fabio Estevam ; David Wolfe ; dwmw2@infradead.org Cc: richard@nod.at; Prabhakar Kushwaha ; Han Xu= ; linux-kernel@vger.kernel.org; linux-spi@vger.kernel.org;= marek.vasut@gmail.com; Frieder Schrempf ; broo= nie@kernel.org; linux-mtd@lists.infradead.org; miquel.raynal@bootlin.com; c= omputersforpeace@gmail.com Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI = controller On Fri, 15 Jun 2018 13:42:12 +0000 Yogesh Narayan Gaur wrote: > Hi Boris, >=20 > I am still debugging the issue. > With some analysis, able to check that proper values are not being writte= n for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register. >=20 > In current code, value of map_addr are being assigned to these register. > map_addr =3D q->memmap_phy + > 2 * q->devtype_data->ahb_buf_size; >=20 > qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4)); >=20 > But instead of "q->devtype_data->ahb_buf_size" it should be flash size. No, because we're only using 2 * ->ahb_buf_size in the direct mapping for e= ach device, and we're modifying the mapping dynamically based on the select= ed device. Maybe we got the logic wrong though. Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need t= o save starting actual address from where this flash is getting started. Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD would ha= ve value of q->memmap_phy + 0x4000000 i.e. (QUADSPI_SFA1AD + sizeof First F= lash) If second flash is of size 32MB, then register QUADSPI_SFB1AD would have va= lue of value of QUADSPI_SFA2AD + sizeof second flash. > For my case flash size is 0x4000000 and with this hard coded value I am a= ble to perform Write and Erase operation. > One more change, I have to do is adding the flash_size when writing the b= ase_address in SFAR register for case when "mem->spi->chip_select =3D=3D 1" > qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR); I don't want to expose the full device in the direct mapping yet (that's pa= rt of the direct-mapping API I posted here [1]). What this version of the d= river does is, map only 2 time the ahb_size so that we can bypass the inter= nal cache of the QSPI engine. To perform any operation on second flash, we need to provide it's base addr= ess should be saved in SFAR register for this particular operation. Exposing only 2 time of ahb_size is design decision but value in SFAR regis= ter should be correct. >=20 > Thus, there should be mechanism or the entry in structure where we can ha= ve the information of the size of the connected slave device. Because that's exactly the kind of thing I'd like to avoid. What if the dev= ice is bigger than the reserved memory region? What if the sum of all devic= es does not fit in there? Here I tried to support all cases by just mapping= the portion of memory we need. So IMO, there should be mechanism to have value of start address of each sl= ave device. This might can be done from DTS entry of each slave device conn= ected to the controller.