Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp4032638imm; Mon, 18 Jun 2018 08:06:01 -0700 (PDT) X-Google-Smtp-Source: ADUXVKL2aFcyDKQYpOMTJ9Lyzw3VIH5RzXtD2TVJHebmM36JzcZ5RkqIAUfLxZjfLm538WYt+hsy X-Received: by 2002:a63:7b4e:: with SMTP id k14-v6mr11374908pgn.261.1529334361450; Mon, 18 Jun 2018 08:06:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529334361; cv=none; d=google.com; s=arc-20160816; b=OE1YgKeRQ384kTOA6gzf7xZL0SOPCMegRl9ttOIo8ougRq0d+T/A3vFhzphcTFT2zr 4q/P0v+iUmI2kniFBkBm7fnAirQZ0K9oUosAsMlzYSK87a+SSub08Hw0TSeIK/nOJ5C9 0RT06z74WvDpgrLC55ij2BFpeTWlf5OmFbhAxkHwbKv2ZLidKO3hzbexSL6cVGYfi/XR HPiaLsXKYlzkwKJC4CUl+Y8Awq20azhtNg3faDgj8ZtNPK22LOvgYtwcDUP1gbRaT1lc E+HpobMdQKV6C9uRBQTAsq/6T4H1hDQaWehq0NDL43aUBA6Iz36VbnhDgK5KpvdlrsmI HJzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=3oOgQg++gaKQtAWcIcSaZQd2ueK925ZOkhQBcUdavZs=; b=y6e18mfHa6TI5ZU8qL75QF7gVO1ReDPriouQ1AnUduGt/QkU9rWfIt3sIHER4tuNhQ pC68r8+dDg51qqvUX8+0wIc7ljYOiywd6TIG4cKQRfr7fA3lVQ1edlF7wY51k44uQT2d /DGcckyZAH2xjQx+qsjMQXbttSmjpckEXYjv8ePqu5dMJ+h1YZQXtiL33lH39NPeTaHY Ovcr6mKN+9eBQTA/uFcwjh73PSJKaxBP78YBxPcWj/Oql4kNKq4iZQ8/CJUm5PMBCM1q PupZN8YsoBKAq95M0ZwcemxRGQXmHNbMB2SRLHSfGdPq0A2MsnH+hpReT3bkzEUNUXYc uicg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@synopsys.com header.s=mail header.b="R/n7k20+"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e11-v6si17235680pln.161.2018.06.18.08.05.44; Mon, 18 Jun 2018 08:06:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@synopsys.com header.s=mail header.b="R/n7k20+"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935515AbeFRPCf (ORCPT + 99 others); Mon, 18 Jun 2018 11:02:35 -0400 Received: from smtprelay.synopsys.com ([198.182.37.59]:42213 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964927AbeFRPBF (ORCPT ); Mon, 18 Jun 2018 11:01:05 -0400 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id AB2661E16CE; Mon, 18 Jun 2018 17:01:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1529334063; bh=wLcHPNjgzoZoCWCaiQdNtA/ikRtPInwCNfw9IKXFSd8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=R/n7k20+LaqTfPCtksBz19Z6+g9zs6NcJsj7BE4bNyqweJ7r3fZfF/976EOtawFIh yz4QvxzbA3Lh8SVgRdkZWFU6+iZsFPYbb+8ESxViP8tGDMD43SzaC7OZ2iHOr04e3w aPJKZ3zgh7qXEdSEQYL3Y6xmg2BxmoN1vghqs4F12lyf7df/THpKVSIW7oopVcXzQo 9Ui7dQrKbcmGcLAA3ipKVtyAelRPWesGZB82IsbdIuw98cppnE1rl5JIAgpNFqPs3s TlhXXkdh9iwTnYeDLQqMMz0IQcXcY8r6jtq0moRgBkizOUJEdqQshCxk951zSr12TF h9lk+qeGBfnog== Received: from pt02.synopsys.com (pt02.internal.synopsys.com [10.107.23.240]) by mailhost.synopsys.com (Postfix) with ESMTP id B4E3A381F; Mon, 18 Jun 2018 08:01:01 -0700 (PDT) Received: from UbuntuMate-64Bits.internal.synopsys.com (gustavo-e7480.internal.synopsys.com [10.107.25.102]) by pt02.synopsys.com (Postfix) with ESMTP id 5FD7C3D75E; Mon, 18 Jun 2018 16:01:00 +0100 (WEST) From: Gustavo Pimentel To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com, adouglas@cadence.com, jesper.nilsson@axis.com Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Gustavo Pimentel Subject: [PATCH v4 06/10] pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace Date: Mon, 18 Jun 2018 16:00:25 +0100 Message-Id: <13077810f3630c01835041e41b338dd85fa91953.1529329262.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away from command section). Signed-off-by: Gustavo Pimentel --- Change v2->v3: - New patch file created base on the previous patch "misc: pci_endpoint_test: Add MSI-X support" patch file following Kishon's suggestion. Change v3->v4: - Rebased to Lorenzo's master branch v4.18-rc1. drivers/misc/pci_endpoint_test.c | 84 ++++++++++++++++----------- drivers/pci/endpoint/functions/pci-epf-test.c | 60 ++++++++++++------- 2 files changed, 91 insertions(+), 53 deletions(-) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 7b37046..56be808 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -35,38 +35,42 @@ #include -#define DRV_MODULE_NAME "pci-endpoint-test" - -#define PCI_ENDPOINT_TEST_MAGIC 0x0 - -#define PCI_ENDPOINT_TEST_COMMAND 0x4 -#define COMMAND_RAISE_LEGACY_IRQ BIT(0) -#define COMMAND_RAISE_MSI_IRQ BIT(1) -#define MSI_NUMBER_SHIFT 2 -/* 6 bits for MSI number */ -#define COMMAND_READ BIT(8) -#define COMMAND_WRITE BIT(9) -#define COMMAND_COPY BIT(10) - -#define PCI_ENDPOINT_TEST_STATUS 0x8 -#define STATUS_READ_SUCCESS BIT(0) -#define STATUS_READ_FAIL BIT(1) -#define STATUS_WRITE_SUCCESS BIT(2) -#define STATUS_WRITE_FAIL BIT(3) -#define STATUS_COPY_SUCCESS BIT(4) -#define STATUS_COPY_FAIL BIT(5) -#define STATUS_IRQ_RAISED BIT(6) -#define STATUS_SRC_ADDR_INVALID BIT(7) -#define STATUS_DST_ADDR_INVALID BIT(8) - -#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc +#define DRV_MODULE_NAME "pci-endpoint-test" + +#define IRQ_TYPE_LEGACY 0 +#define IRQ_TYPE_MSI 1 + +#define PCI_ENDPOINT_TEST_MAGIC 0x0 + +#define PCI_ENDPOINT_TEST_COMMAND 0x4 +#define COMMAND_RAISE_LEGACY_IRQ BIT(0) +#define COMMAND_RAISE_MSI_IRQ BIT(1) +#define COMMAND_READ BIT(3) +#define COMMAND_WRITE BIT(4) +#define COMMAND_COPY BIT(5) + +#define PCI_ENDPOINT_TEST_STATUS 0x8 +#define STATUS_READ_SUCCESS BIT(0) +#define STATUS_READ_FAIL BIT(1) +#define STATUS_WRITE_SUCCESS BIT(2) +#define STATUS_WRITE_FAIL BIT(3) +#define STATUS_COPY_SUCCESS BIT(4) +#define STATUS_COPY_FAIL BIT(5) +#define STATUS_IRQ_RAISED BIT(6) +#define STATUS_SRC_ADDR_INVALID BIT(7) +#define STATUS_DST_ADDR_INVALID BIT(8) + +#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 -#define PCI_ENDPOINT_TEST_SIZE 0x1c -#define PCI_ENDPOINT_TEST_CHECKSUM 0x20 +#define PCI_ENDPOINT_TEST_SIZE 0x1c +#define PCI_ENDPOINT_TEST_CHECKSUM 0x20 + +#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 +#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 static DEFINE_IDA(pci_endpoint_test_ida); @@ -179,6 +183,9 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) { u32 val; + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, + IRQ_TYPE_LEGACY); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0); pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, COMMAND_RAISE_LEGACY_IRQ); val = wait_for_completion_timeout(&test->irq_raised, @@ -190,20 +197,22 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) } static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, - u8 msi_num) + u8 irq_num) { u32 val; struct pci_dev *pdev = test->pdev; + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, + IRQ_TYPE_MSI); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, irq_num); pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, - msi_num << MSI_NUMBER_SHIFT | COMMAND_RAISE_MSI_IRQ); val = wait_for_completion_timeout(&test->irq_raised, msecs_to_jiffies(1000)); if (!val) return false; - if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq) + if (pci_irq_vector(pdev, irq_num - 1) == test->last_irq) return true; return false; @@ -281,8 +290,11 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size) pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, + no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, - 1 << MSI_NUMBER_SHIFT | COMMAND_COPY); + COMMAND_COPY); wait_for_completion(&test->irq_raised); @@ -348,8 +360,11 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size) pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, + no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, - 1 << MSI_NUMBER_SHIFT | COMMAND_READ); + COMMAND_READ); wait_for_completion(&test->irq_raised); @@ -403,8 +418,11 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size) pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, + no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, - 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE); + COMMAND_WRITE); wait_for_completion(&test->irq_raised); diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 63ed706..ff92524 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -18,13 +18,14 @@ #include #include +#define IRQ_TYPE_LEGACY 0 +#define IRQ_TYPE_MSI 1 + #define COMMAND_RAISE_LEGACY_IRQ BIT(0) #define COMMAND_RAISE_MSI_IRQ BIT(1) -#define MSI_NUMBER_SHIFT 2 -#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT) -#define COMMAND_READ BIT(8) -#define COMMAND_WRITE BIT(9) -#define COMMAND_COPY BIT(10) +#define COMMAND_READ BIT(3) +#define COMMAND_WRITE BIT(4) +#define COMMAND_COPY BIT(5) #define STATUS_READ_SUCCESS BIT(0) #define STATUS_READ_FAIL BIT(1) @@ -56,6 +57,8 @@ struct pci_epf_test_reg { u64 dst_addr; u32 size; u32 checksum; + u32 irq_type; + u32 irq_number; } __packed; static struct pci_epf_header test_header = { @@ -244,31 +247,39 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) return ret; } -static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq) +static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type, + u16 irq) { - u8 msi_count; struct pci_epf *epf = epf_test->epf; + struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; enum pci_barno test_reg_bar = epf_test->test_reg_bar; struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg->status |= STATUS_IRQ_RAISED; - msi_count = pci_epc_get_msi(epc, epf->func_no); - if (irq > msi_count || msi_count <= 0) + + switch (irq_type) { + case IRQ_TYPE_LEGACY: pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0); - else + break; + case IRQ_TYPE_MSI: pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq); + break; + default: + dev_err(dev, "Failed to raise IRQ, unknown type\n"); + break; + } } static void pci_epf_test_cmd_handler(struct work_struct *work) { int ret; - u8 irq; - u8 msi_count; + u16 count; u32 command; struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test, cmd_handler.work); struct pci_epf *epf = epf_test->epf; + struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; enum pci_barno test_reg_bar = epf_test->test_reg_bar; struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; @@ -280,7 +291,10 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) reg->command = 0; reg->status = 0; - irq = (command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT; + if (reg->irq_type > IRQ_TYPE_MSI) { + dev_err(dev, "Failed to detect IRQ type\n"); + goto reset_handler; + } if (command & COMMAND_RAISE_LEGACY_IRQ) { reg->status = STATUS_IRQ_RAISED; @@ -294,7 +308,8 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) reg->status |= STATUS_WRITE_FAIL; else reg->status |= STATUS_WRITE_SUCCESS; - pci_epf_test_raise_irq(epf_test, irq); + pci_epf_test_raise_irq(epf_test, reg->irq_type, + reg->irq_number); goto reset_handler; } @@ -304,7 +319,8 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) reg->status |= STATUS_READ_SUCCESS; else reg->status |= STATUS_READ_FAIL; - pci_epf_test_raise_irq(epf_test, irq); + pci_epf_test_raise_irq(epf_test, reg->irq_type, + reg->irq_number); goto reset_handler; } @@ -314,16 +330,18 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) reg->status |= STATUS_COPY_SUCCESS; else reg->status |= STATUS_COPY_FAIL; - pci_epf_test_raise_irq(epf_test, irq); + pci_epf_test_raise_irq(epf_test, reg->irq_type, + reg->irq_number); goto reset_handler; } if (command & COMMAND_RAISE_MSI_IRQ) { - msi_count = pci_epc_get_msi(epc, epf->func_no); - if (irq > msi_count || msi_count <= 0) + count = pci_epc_get_msi(epc, epf->func_no); + if (reg->irq_number > count || count <= 0) goto reset_handler; reg->status = STATUS_IRQ_RAISED; - pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq); + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, + reg->irq_number); goto reset_handler; } @@ -457,8 +475,10 @@ static int pci_epf_test_bind(struct pci_epf *epf) return ret; ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts); - if (ret) + if (ret) { + dev_err(dev, "MSI configuration failed\n"); return ret; + } if (!epf_test->linkup_notifier) queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work); -- 2.7.4