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[209.132.180.67]) by mx.google.com with ESMTP id m3-v6si13681789pgu.237.2018.06.19.01.38.40; Tue, 19 Jun 2018 01:38:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=dtYiIfl9; dkim=pass header.i=@codeaurora.org header.s=default header.b=NU1H+Xl9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965191AbeFSIhE (ORCPT + 99 others); Tue, 19 Jun 2018 04:37:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49626 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937229AbeFSIhB (ORCPT ); Tue, 19 Jun 2018 04:37:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 97F5F60714; Tue, 19 Jun 2018 08:37:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529397420; bh=/q1z3Zl2O8+ScyZGea0qzPlLE2B9Q7VRkETsjSVYr28=; h=From:To:Cc:Subject:Date:From; b=dtYiIfl9p+FJoVd+HrVLEhqbTpnigveCmX8rphQR+t1Z7VhmSsnoSeK4TKXncWPFo oIJ328DgUQ4skXqW2JokTXixjQyLNStHICxy9765p/8uaAXJWXLkztgGm2iK/IcTGA +Cl/Sxrbn51yDER78un8Pvm9BoJG+E8KLLtvPRcU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from CANG02.ap.qualcomm.com (unknown [180.166.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cang@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7EF9C60227; Tue, 19 Jun 2018 08:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1529397419; bh=/q1z3Zl2O8+ScyZGea0qzPlLE2B9Q7VRkETsjSVYr28=; h=From:To:Cc:Subject:Date:From; b=NU1H+Xl9pm3iK4LexVbfFhpp2MV0ziiPOjMsR4mPCwQVqD0k017ic6UEChu50IVIj pnvAeHYpgjPQrNJcQOttW162dWdTzKme+GnBvC8tBU+/Mxgk6zxgF6ZBSi54twO+H3 9+0fGvUP3ol78arnC6O8h8ioVXsh8v9/Iu0ybZc8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7EF9C60227 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cang@codeaurora.org From: Can Guo To: subhashj@codeaurora.org, asutoshd@codeaurora.org, vivek.gautam@codeaurora.org, mgautam@codeaurora.org, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Can Guo Subject: [PATCH v7 0/4] Support for Qualcomm UFS QMP PHY on SDM845 Date: Tue, 19 Jun 2018 16:36:43 +0800 Message-Id: <20180619083647.10116-1-cang@codeaurora.org> X-Mailer: git-send-email 2.15.0.windows.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series adds support for UFS QMP PHY on SDM845 and the compatible string for it. This patch series depends on the current proposed QMP V3 USB3 UNI PHY support for sdm845 driver [1], on the DT bindings for the QMP V3 USB3 PHYs based dirver [2], and also rebased on updated pipe_clk initialization sequence [3]. This series can only be merged once the dependent patches do. [1] http://lists-archives.com/linux-kernel/29071659-dt-bindings-phy-qcom-qmp-update-bindings-for-sdm845.html [2] http://lists-archives.com/linux-kernel/29071660-phy-qcom-qmp-add-qmp-v3-usb3-uni-phy-support-for-sdm845.html [3] https://patchwork.kernel.org/patch/10376551/ Changes since v6: - Add one new change to clean up some structs and field - Updates the PHY power control sequence. - Incorporated review comments from Vivek and Manu. Changes since v5: - Updates the PHY power control sequence. - Updates UFS PHY power on condition check. Changes since v4: - Adds 'ref_aux' clock back to SDM845 UFS PHY clock list. - Power on PHY before serdes configuration starts. - Updates the UFS PHY initialization sequence. - Updates a few UFS PHY registers. - Incorporated review comments from Vivek and Manu. Changes since v3: - Incorporated review comments from Vivek and Rob. Changes since v2: - Incorporated review comments from Vivek and Rob. - Remove "ref_aux" from sdm845 ufs phy clock list structure. Changes since v1: - Incorporated review comments from Vivek and Manu. - Update the commit title of patch 2. Can Guo (4): phy: Update PHY power control sequence phy: General struct and field cleanup phy: Add QMP phy based UFS phy support for sdm845 dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845 .../devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +- drivers/phy/qualcomm/phy-qcom-qmp.c | 217 +++++++++++++++++++-- drivers/phy/qualcomm/phy-qcom-qmp.h | 15 ++ 3 files changed, 216 insertions(+), 20 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project