Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp120173imm; Tue, 19 Jun 2018 17:19:31 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK3uumfzOVUUdlH6dEnPwnmz+laSBElJpLcr6viQu/egkJHSOYrz3y82Dwvaqy3TOfFZEUL X-Received: by 2002:a17:902:6903:: with SMTP id j3-v6mr20774829plk.313.1529453971602; Tue, 19 Jun 2018 17:19:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529453971; cv=none; d=google.com; s=arc-20160816; b=DrAHd3CeolSr3wRhndYEmw0LI0FlyX5jH57yWAosUeXxYIA0eO1EBB7v8wNIgTzLQ1 jel5lYgoaMX/mkWIGNTuyT0LlnJlq8gSzinGkGDGYy0F6G14jp+GQmKN7EpPRfRU7s1H pgMOHssHlVEZ6owbuecg0zGkYyIDgGMH+8vbC2yx7944vUfsiZX8oxvJSj7DleosEtIB 5icvYJTt7FkDufmCqz0nlPWS65fbol4BbL1e2NOxHzZfv3kzaK4WDqobh2g0WDEwsBwU qB4YJFyKFr7YA7J/F1J4/UvoKhNXs2hZDBdNlE/RpOX5AaleqU1cFCVkhXXSU1LfDJN9 kTBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id :arc-authentication-results; bh=2k0ZDMbD9PSN/p6MZSV2MgZ3bwb1J3uHAbcYzxCYaOI=; b=sqaC84Hb/t7vn6lbIG5t0RnZly28FS0FyEro69+6oDaiYVG1qijEYKHXskOGjfttVX iGOD0LXwg/0uVS9S8nlAEArWl4iTc6P/HZGhChh/TXwXv2ZPYV8DyC9GqZjo0wJknc8v 6XQEBRio8+C85xTEFG57Oqj7wcQuxmuLKtDP+nbBiTM9v7/Z9ewiMPJyceLiyHO1o092 DkWsZ8GL7A13lf5Z5gjXle4RC4XWmlloLS+LmWrUZiCzrTKao9VPE6i5Uuyby3SbZFUd EI7ecQVsluIZtXs0291dNy2+qdfsU3uJgiR7FVquUxPDDof158Jz2+wBRQCUVm1V7vzy cHFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a34-v6si927426pld.281.2018.06.19.17.19.17; Tue, 19 Jun 2018 17:19:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754162AbeFTAST (ORCPT + 99 others); Tue, 19 Jun 2018 20:18:19 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53347 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753644AbeFTASP (ORCPT ); Tue, 19 Jun 2018 20:18:15 -0400 X-UUID: 905c31c909fa4d269f033ba9d37e0c80-20180620 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 706182493; Wed, 20 Jun 2018 08:18:09 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 20 Jun 2018 08:18:07 +0800 Received: from [172.21.77.33] (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 20 Jun 2018 08:18:07 +0800 Message-ID: <1529453887.8701.0.camel@mtkswgap22> Subject: Re: [PATCH 2/2] arm64: dts: mediatek: add mt6765 support From: Mars Cheng To: Matthias Brugger CC: Rob Herring , CC Hwang , "Loda Chou" , Miles Chen , "Jades Shih" , Yingjoe Chen , My Chuang , , , , Date: Wed, 20 Jun 2018 08:18:07 +0800 In-Reply-To: <80bca2ae-eb08-3d6c-a863-140107286b2d@gmail.com> References: <1528843243-29782-1-git-send-email-mars.cheng@mediatek.com> <1528843243-29782-3-git-send-email-mars.cheng@mediatek.com> <80bca2ae-eb08-3d6c-a863-140107286b2d@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias On Fri, 2018-06-15 at 10:54 +0200, Matthias Brugger wrote: > > On 13/06/18 00:40, Mars Cheng wrote: > > + > > + uart0: serial@11002000 { > > + compatible = "mediatek,mt6765-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11002000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > You need "baud" and "bus" clock. Also add clock-names please. Got it, will add them in V2 > > > + > > + uart1: serial@11003000 { > > + compatible = "mediatek,mt6765-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11003000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > Same here obviously. Will fixed in V2. Thanks. > > Regards, > Matthias