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[209.132.180.67]) by mx.google.com with ESMTP id d34-v6si4349104pld.252.2018.06.21.02.04.59; Thu, 21 Jun 2018 02:05:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932813AbeFUJDp (ORCPT + 99 others); Thu, 21 Jun 2018 05:03:45 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:49712 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754367AbeFUJDJ (ORCPT ); Thu, 21 Jun 2018 05:03:09 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w5L8wvw3031674; Thu, 21 Jun 2018 11:02:34 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2jqqgqc617-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Jun 2018 11:02:34 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0D2E738; Thu, 21 Jun 2018 09:02:32 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E91472652; Thu, 21 Jun 2018 09:02:31 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.94) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Jun 2018 11:02:31 +0200 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Jun 2018 11:02:31 +0200 From: Ludovic Barre To: Wim Van Sebroeck , Guenter Roeck , Rob Herring CC: Maxime Coquelin , Alexandre Torgue , , , , , Ludovic Barre Subject: [PATCH V4 4/4] ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1 Date: Thu, 21 Jun 2018 11:02:17 +0200 Message-ID: <1529571737-3552-5-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529571737-3552-1-git-send-email-ludovic.Barre@st.com> References: <1529571737-3552-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-06-21_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ludovic Barre This patch activates independent watchdog support for stm32mp157c board. Signed-off-by: Ludovic Barre --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index ae33653..8af263a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -68,6 +68,11 @@ status = "okay"; }; +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; -- 2.7.4