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[109.80.100.85]) by smtp.gmail.com with ESMTPSA id v10-v6sm10807079wrn.97.2018.06.22.04.25.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Jun 2018 04:25:59 -0700 (PDT) Date: Fri, 22 Jun 2018 13:25:53 +0200 From: Andrea Parri To: Will Deacon Cc: Peter Zijlstra , Alan Stern , LKMM Maintainers -- Akira Yokosawa , Boqun Feng , David Howells , Jade Alglave , Luc Maranget , Nicholas Piggin , "Paul E. McKenney" , Kernel development list Subject: Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks Message-ID: <20180622112553.GA10658@andrea> References: <20180622080928.GB7601@arm.com> <20180622095547.GE7601@arm.com> <20180622103129.GQ2476@hirez.programming.kicks-ass.net> <20180622103838.GF7601@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180622103838.GF7601@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > > I also just realised that this prevents Power from using ctrl+isync to > > > implement acquire, should they wish to do so. > > > > They in fact do so on chips lacking LWSYNC, see how PPC_ACQUIRE_BARRIER > > (as used by atomic_*_acquire) turns into ISYNC (note however that they > > do not use PPC_ACQUIRE_BARRIER for smp_load_acquire -- because there's > > no CTRL there). > > Right, so the example in the commit message is broken on PPC then. I think > it's also broken on RISC-V, despite the claim. I agree for RISC-V (and I missed it in my earlier review): the 2nd snippet from the commit message would map to something like fence rw, w STORE #1,[x] LOAD [x] fence r ,rw STORE #1,[y] and there would be no guarantee that the stores to x and y will be propagated in program order to another CPU, AFAICT. Thank you for pointing this out. Andrea