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From:   Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
To:     Marc Zyngier <marc.zyngier@arm.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Thomas Gleixner <tglx@linutronix.de>,
        Ard Biesheuvel <ard.biesheuvel@linaro.org>,
        Shanker Donthineni <shankerd@codeaurora.org>,
        Laurentiu Tudor <laurentiu.tudor@nxp.com>,
        Lei Zhang <zhang.lei@jp.fujitsu.com>,
        Linuxarm <linuxarm@huawei.com>
Subject: RE: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI
 range
Thread-Topic: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI
 range
Thread-Index: AQHUCJ4hzL+MVAKZUUSRAob8n9It1KRseE1Q
Date:   Fri, 22 Jun 2018 16:31:40 +0000
Message-ID: <5FC3163CFD30C246ABAA99954A238FA838706A1B@FRAEML521-MBX.china.huawei.com>
References: <20180620135234.32101-1-marc.zyngier@arm.com>
 <20180620135234.32101-7-marc.zyngier@arm.com>
In-Reply-To: <20180620135234.32101-7-marc.zyngier@arm.com>
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Hi Marc,

> -----Original Message-----
> From: Marc Zyngier [mailto:marc.zyngier@arm.com]
> Sent: 20 June 2018 14:53
> To: linux-kernel@vger.kernel.org
> Cc: Thomas Gleixner <tglx@linutronix.de>; Ard Biesheuvel
> <ard.biesheuvel@linaro.org>; Shanker Donthineni
> <shankerd@codeaurora.org>; Shameerali Kolothum Thodi
> <shameerali.kolothum.thodi@huawei.com>; MaJun <majun258@huawei.com>;
> Laurentiu Tudor <laurentiu.tudor@nxp.com>; Lei Zhang
> <zhang.lei@jp.fujitsu.com>
> Subject: [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI range
> 
> A recent extension to the GIC architecture allows a hypervisor to
> arbitrarily reduce the number of LPIs available to a guest, no
> matter what the GIC says about the valid range of IntIDs.
> 
> Let's factor in this information when computing the number of
> available LPIs

On our D05 board, this limits the lpis to 2 and results in MSI irq alloc fails:

[    0.000000] ITS: Using hypervisor restricted LPI range [2]
....
[   10.543889] ixgbe 000a:11:00.1: Failed to allocate MSI interrupt, falling back to legacy. Error: -12
 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  drivers/irqchip/irq-gic-v3-its.c   | 9 +++++++++
>  include/linux/irqchip/arm-gic-v3.h | 1 +
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 8c7e8c235faf..903ca1c19553 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1525,8 +1525,17 @@ static int free_lpi_range(u32 base, u32 nr_lpis)
>  static int __init its_lpi_init(u32 id_bits)
>  {
>  	u32 lpis = (1UL << id_bits) - 8192;
> +	u32 numlpis;
>  	int err;
> 
> +	numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
> +
> +	if (numlpis > 1 && !WARN_ON(numlpis > lpis)) {
> +		lpis = numlpis;
> +		pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
> +			lpis);
> +	}

I don't have the GICv3 extension doc, but did you intent to check for,

 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {

as it looks like D05 returns 0 for bits 11-15 and that makes numlpis=2.

Please let me know.

Thanks,
Shameer

> +
>  	/*
>  	 * Initializing the allocator is just the same as freeing the
>  	 * full range of LPIs.
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-
> v3.h
> index 396cd99af02f..9d2ea3e907d0 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -73,6 +73,7 @@
>  #define GICD_TYPER_MBIS			(1U << 16)
> 
>  #define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)
> +#define GICD_TYPER_NUM_LPIS(typer)	((((typer) >> 11) & 0x1f) + 1)
>  #define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)
> 
>  #define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
> --
> 2.17.1