Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp1382358imm; Fri, 22 Jun 2018 15:58:27 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJDaqctEniaMowVqC27Rpd7M1jWeYt5ihC04uoZyrtCRbTprvGae3Mb3SRG6wK+WYlfkxS6 X-Received: by 2002:a65:6612:: with SMTP id w18-v6mr2938463pgv.38.1529708307428; Fri, 22 Jun 2018 15:58:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529708307; cv=none; d=google.com; s=arc-20160816; b=UZWjLd7/LIy62OeniC+y0btj8ckQvk4dG6T0KBNrdWND5O8G1FpdTmyHqvj+vJL39N Svr5H5o4aLaDyOc91ubvNyNyJzyRd6J2bhihdbPSpqDgXdLeGmSPigxcFqErejpAhNph YJROfXakQhBZ6V6PiSKSXTntHAU7m0kSMcLGZMUq62cJJKI3xsgBBK5X1P/CRHuyMtEv IZaBTPma2VdNIInmW6x+I3JlQ1+uRyaoVT5cJXRr+jE9IrA8qkIRJT8Tu3AIm58uiasv GC+G9CjLkS88uI00RmI7XlmtJnmDbhllatzJ/NWGe8Y0SEvRR6Lwwl0y6YXELd2IgpIG rMjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:user-agent:references :message-id:in-reply-to:subject:cc:to:from:date :arc-authentication-results; bh=YfTZvm79o7mt7zfvD6nLMNOyYGQRVAiqDC5hmBWvfAE=; b=BmVKf7hX1vzNcYPFoh22TNXOrgxmYepqVeaAk6Diryr3CcScP7Qox1qkPlEXES32E8 GBUie3RG6gO6oNCWPpAvW4+z+CRoEPUQU5CQvbDcKs6aEg9YU13nc85OP44ekqFSoJgJ Hm9Qf+H5lcR8IlecGi/yGngKsbTi/+EfrzirEmvrDkLzfKxZn51k2XmrhDyNttk51cP/ QydN604idFiV3Z71Bg9gsImuW7O7hcJzay8nVtoDnxB0K1bSfoj7WVM2w79PS3BRyJHT 3FSf5I50GaDMRtWR2FsFqxpU5HihsEo4v0EcFLEFijEb1mPnQbsSnN/oiAIfD1oj8KYQ wz/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z3-v6si8207379plb.228.2018.06.22.15.58.12; Fri, 22 Jun 2018 15:58:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754646AbeFVW5b (ORCPT + 99 others); Fri, 22 Jun 2018 18:57:31 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:42971 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754184AbeFVW5a (ORCPT ); Fri, 22 Jun 2018 18:57:30 -0400 Received: from p4fea482e.dip0.t-ipconnect.de ([79.234.72.46] helo=nanos.glx-home) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fWUzX-00056V-N5; Sat, 23 Jun 2018 00:57:19 +0200 Date: Sat, 23 Jun 2018 00:57:19 +0200 (CEST) From: Thomas Gleixner To: Fenghua Yu cc: Ingo Molnar , "H. Peter Anvin" , Ashok Raj , Dave Hansen , Rafael Wysocki , Tony Luck , Alan Cox , Ravi V Shankar , Arjan van de Ven , linux-kernel , x86 Subject: Re: [RFC PATCH 02/16] x86/split_lock: Handle #AC exception for split lock in kernel mode In-Reply-To: <20180622224154.GD18979@romley-ivt3.sc.intel.com> Message-ID: References: <1527435965-202085-1-git-send-email-fenghua.yu@intel.com> <1527435965-202085-3-git-send-email-fenghua.yu@intel.com> <20180622224154.GD18979@romley-ivt3.sc.intel.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 22 Jun 2018, Fenghua Yu wrote: > On Fri, Jun 22, 2018 at 01:59:44PM +0200, Thomas Gleixner wrote: > > Aside of that the spec says: > > > > 31 Disable LOCK# assertion for split locked access. > > > > Can you pretty please make sure that this bit enforces #AC enable? If 31 is > > ever set and such an access happens then the resulting havoc will takes > > ages to decode. > > > > That bit is also mentioned in the SDM with ZERO explanation why it exists > > in the first place and why anyone would ever enable it and without a big > > fat warning about the possible consequences. Can this pretty please be > > fixed? > > The bit 31 already exits on all processors. Hardware always sets its value > as zero after power on. It has been legacy for 20 years. It was added for > one customer 20 years ago. Now Intel hardware design team doesn't expect > anyone to set the bit. Doesn't expect. ROTFL. That's the most stupiest excuse for not adding a big fat warning into the SDM why this abomination should never be used at all. Aside of that does the Intel hardware design team expect that this one customer is still depending on this nonsense and is therefore proliferating it forever? > Currently Linux kernel doesn't define this bit and doesn't set this bit. Thanks for the education. I knew that already, but it still does not make the existence of it in contemporary CPUs any better or more justified. Thanks, tglx