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[209.132.180.67]) by mx.google.com with ESMTP id 139-v6si13063493pfw.254.2018.06.24.15.46.18; Sun, 24 Jun 2018 15:46:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@alliedtelesis.co.nz header.s=mail header.b=li02eAdm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=alliedtelesis.co.nz Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752233AbeFXWpG (ORCPT + 99 others); Sun, 24 Jun 2018 18:45:06 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:56238 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751945AbeFXWpC (ORCPT ); Sun, 24 Jun 2018 18:45:02 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 1BD0D8364E; Mon, 25 Jun 2018 10:44:59 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1529880299; bh=kBq5H60Y0BQYRQGG4JDfLIKp0eP+BvPKeCq1BOdRxwc=; h=From:To:Cc:Subject:Date; b=li02eAdmrmYuUwxKGSBaQPG1Y+ODynyrSkWOt3uRPDhjzu7sj84qSugSawjH8I5+V 5DSUwz0cY5JamtrnCpNSEQxUy3MsFjztylxygbaJ4kCxs7Tc4/LLWdQ5VKpvzMJTiz JgbyLnmTFPnhVWdNm8XBVzVkfQLE6ejUM9dyPlGM= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Mon, 25 Jun 2018 10:44:58 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 17DC713EE1C; Mon, 25 Jun 2018 10:44:57 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A582A1E2626; Mon, 25 Jun 2018 10:44:53 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, boris.brezillon@bootlin.com, dwmw2@infradead.org, computersforpeace@gmail.com, linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v6 0/6] mtd: rawnand: support MT29F1G08ABAFAWP-ITE:F Date: Mon, 25 Jun 2018 10:44:42 +1200 Message-Id: <20180624224448.21872-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.18.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip to one of our boards which uses the Marvell NFCv2 controller. This particular chip is a bit odd in that the datasheet states support for ONFI 1.0 but the revision number field is 00 00. It also is marked ABAFA but reports internally as ABAGA. Finally it has internal 8-bit ECC which cannot be disabled. The existing test in micron_supports_on_die_ecc() determines that on-die ECC is supported but not mandatory but I know for this chip it is mandatory despite what set_features returns. In order for this to work I need to set nand-ecc-mode = "on-die" in my dts. Ideally I'd like it to be automatic based on what the hardware can support but that may be asking too much at the moment. Here's a dump of the parameter page from the chip I have 00000000: 4f 4e 46 49 00 00 18 00 3f 00 00 00 00 00 00 00 ONFI....?....... 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00000020: 4d 49 43 52 4f 4e 20 20 20 20 20 20 4d 54 32 39 MICRON MT29 00000030: 46 31 47 30 38 41 42 41 47 41 57 50 20 20 20 20 F1G08ABAGAWP 00000040: 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ,............... 00000050: 00 08 00 00 80 00 00 02 00 00 20 00 40 00 00 00 .......... .@... 00000060: 00 04 00 00 01 22 01 14 00 01 05 08 00 00 04 00 .....".......... 00000070: 08 01 0e 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00000080: 08 3f 00 3f 00 58 02 10 27 46 00 64 00 00 00 00 .?.?.X..'F.d.... 00000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000a0: 00 00 00 00 01 00 00 00 00 02 04 80 01 81 04 03 ................ 000000b0: 02 01 1e 90 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 85 a6 ................ Series changes in v3: - No longer RFC - dropped "mtd: rawnand: micron: add ONFI_FEATURE_ON_DIE_ECC to supported features" which Boris has already picked up - dropped "mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC" since I can't test it. Series changes in v4: - based on top of http://patchwork.ozlabs.org/patch/932006/ Series changes in v5: - address review comments from Boris on patches 5 and 6 Series changes in v6: - Update commit message on 6/6 Chris Packham (6): mtd: rawnand: marvell: Handle on-die ECC mtd: rawnand: add manufacturer fixup for ONFI parameter page mtd: rawnand: add defines for ONFI version bits mtd: rawnand: micron: add fixup for ONFI revision mtd: rawnand: micron: support 8/512 on-die ECC mtd: rawnand: micron: detect forced on-die ECC drivers/mtd/nand/raw/marvell_nand.c | 1 + drivers/mtd/nand/raw/nand_base.c | 14 +-- drivers/mtd/nand/raw/nand_micron.c | 129 +++++++++++++++++++++++----- include/linux/mtd/rawnand.h | 14 +++ 4 files changed, 131 insertions(+), 27 deletions(-) -- 2.18.0