Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp3635462imm; Mon, 25 Jun 2018 01:52:33 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIl1pJRA4B/RFLOedooy21kTKpoIrps+snYns/+5lFnfWqNINtI+skXD2G1s2/KIUXAnzmw X-Received: by 2002:a62:5a45:: with SMTP id o66-v6mr1280029pfb.86.1529916753201; Mon, 25 Jun 2018 01:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529916753; cv=none; d=google.com; s=arc-20160816; b=LmyK+vwnbOvZxnw/QmlYSdo7tcEqQOCYRZ0fti6LhA7XHqW2fBRlaDzn1QfcqHeoUg XDAHf+Oipk0jRXP0xhxZ2a/OutIXABt1t8X6Fy3DP+KNDu8Rk0guUZhhjOFxRBmH1WoS POqsurUvzb5zjrwWbVaLgjivEPPJeNRZ5iZAZez1Y4FCr5uPimU6iWyArFs/9HnkOpR9 SoRlWtj2M+84m3WsYBKNPAv0klgWwtt5EQThhyUskWyeC1oKJCfMCKJAjVxukTvexmv8 etkQF14YIetAd3eHylGF+wIDfsSFovjHLaXg/nP6CX3IcKZPNUCyjQpSx5a5aSYGexQr x98Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=qV04DcHjIYomQhdftvovwXcyT57Pa/uNcBg5V82DQFo=; b=KvgZ5d6WKHdjNHj034cMyo3HVC82NaXFBv5HRjoMeO1hE6p8J8PWQEAAFic+s4nemB 7J6kkEjdPW4k+Yqr1oApQQY6sgEBPaD7PdsRTaMAImfl7D2MYWwdixhYTRmExGghxIf1 SMTn7/9P+QGXGs/x6rBkCjBueiXzw8FJbMY1YnRt3mtySEO83AGzDKKcCkgONqF4cVTq TSAgL5/5EZQSyM5mN0/2htWripBqFZUt4em4iOAYxrT/CH0D3YyIS8m6k2WV6weY+iIG w/onApAWVIYuHukLldwB+STb6eM/HzosAzN/aniviA+w9nujXM5EydaeW1+qBG4CqND4 dsjQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ca5-v6si13860571plb.143.2018.06.25.01.52.18; Mon, 25 Jun 2018 01:52:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754654AbeFYIu7 (ORCPT + 99 others); Mon, 25 Jun 2018 04:50:59 -0400 Received: from exmail.andestech.com ([59.124.169.137]:36860 "EHLO ATCSQR.andestech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754245AbeFYIu6 (ORCPT ); Mon, 25 Jun 2018 04:50:58 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id w5P8qhrk009416; Mon, 25 Jun 2018 16:52:43 +0800 (GMT-8) (envelope-from zong@andestech.com) Received: from atcsqa06.andestech.com (10.0.1.85) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Mon, 25 Jun 2018 16:50:00 +0800 From: Zong Li To: , , , , CC: Zong Li , Subject: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Date: Mon, 25 Jun 2018 16:49:39 +0800 Message-ID: <4c4def99db5e0392238947dc878c5018cc7aca3e.1529915117.git.zong@andestech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.0.1.85] X-DNSRBL: X-MAIL: ATCSQR.andestech.com w5P8qhrk009416 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li --- arch/riscv/include/uapi/asm/elf.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index 5cae4c30cd8e..1e0dfc36aab9 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -21,8 +21,13 @@ typedef struct user_regs_struct elf_gregset_t; typedef union __riscv_fp_state elf_fpregset_t; -#define ELF_RISCV_R_SYM(r_info) ((r_info) >> 32) -#define ELF_RISCV_R_TYPE(r_info) ((r_info) & 0xffffffff) +#if __riscv_xlen == 64 +#define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info) +#define ELF_RISCV_R_TYPE(r_info) ELF64_R_TYPE(r_info) +#else +#define ELF_RISCV_R_SYM(r_info) ELF32_R_SYM(r_info) +#define ELF_RISCV_R_TYPE(r_info) ELF32_R_TYPE(r_info) +#endif /* * RISC-V relocation types -- 2.16.1