Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp4754869imm; Mon, 25 Jun 2018 23:23:42 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJf4lgpyFnxdBku5is8dB7rCOcfCyCrzQwthqhRsTCOjPI4P7EFzjKz6GwGFXIl/ACDmIi9 X-Received: by 2002:a65:6455:: with SMTP id s21-v6mr183960pgv.394.1529994222790; Mon, 25 Jun 2018 23:23:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529994222; cv=none; d=google.com; s=arc-20160816; b=ZFA+lV9CLmTO/TUai4EfY0DspaMpp3TfNirmM8jZ3+A+AB6uhPDQSzJuVMTxxqBfBU kFr9SfE6zonKhpxmGrmk3VSYuxKRr4AaWdqkU2RLWc//Lg8bGZDyro+vooogZc8AvGoB XVHPAvpI4mx6PNkXGKhlIt2xznzyIHb/t1HCyjlZ9vfMnN7/EdR2Mrm62WQydxETGInP Xkokajgqw8Zy3/fFlylZvj9Wh9JYh75ahbwv92D8pm16SwC9jwEj4MUxmEBcjwHnuBZT 2n5Z9y5R5fzXtgmvHE1JqTHGSehVbmo0naTtzX/y+OroD9krjCGGrGhT6cB+ippwIu4/ GeAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=E4oE5a8RfYBGqTE5UNEk9RnwD/IIFMCaqDeHwl/4zok=; b=l5SW7TCcmNhjCBRJyqQPd8eP/gejejvWEAg6bnq2crvqUPssE/TzhmiI/NKfHaf6mL WJkmptW176ROtyOX0ZN7mN87/QjO3Amzt+lwgx1l2BbV521hunIOpm/iGROBqsxEDDk6 GjizrVxPadZzOgvCNSUoklbtnm8y0wzE+qiaAEDScM2flthwnOz3OI6r4PP+4sGyJ068 Vuso/E5p2FxwDb1InZUgs2TX1c8i4qTuiqHLChkb/AeBHkYDII8EGjxZ0hhIgB84eBnL Q9JooHYlFVLn3YKTuryjz9mhWJXEeNxT5Kx1bOsJpZQR9HdHD+uck3hVl2yghsEwRLWa DGdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 139-v6si779015pgc.87.2018.06.25.23.23.26; Mon, 25 Jun 2018 23:23:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752031AbeFZGWc (ORCPT + 99 others); Tue, 26 Jun 2018 02:22:32 -0400 Received: from mga09.intel.com ([134.134.136.24]:51873 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbeFZGWb (ORCPT ); Tue, 26 Jun 2018 02:22:31 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jun 2018 23:22:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,273,1526367600"; d="scan'208";a="240651371" Received: from shawn-bm6650-bm6350.itwn.intel.com ([10.5.253.27]) by fmsmga006.fm.intel.com with ESMTP; 25 Jun 2018 23:22:27 -0700 From: alanx.chiang@intel.com To: linux-i2c@vger.kernel.org Cc: andy.yeh@intel.com, sakari.ailus@linux.intel.com, andriy.shevchenko@intel.com, rajmohan.mani@intel.com, andy.shevchenko@gmail.com, brgl@bgdev.pl, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, "alanx.chiang" Subject: [PATCH v2 1/2] dt-bindings: at24: Add address-width property Date: Tue, 26 Jun 2018 14:22:07 +0800 Message-Id: <1529994128-26770-2-git-send-email-alanx.chiang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> References: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "alanx.chiang" The AT24 series chips use 8-bit address by default. If some chips would like to support more than 8 bits, should add the compatible field for specfic chips in the driver. Provide a flexible way to determine the addressing bits through address-width in this patch. Signed-off-by: Alan Chiang Signed-off-by: Andy Yeh --- since v1: -- Remove the address-width field in the example. --- Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index 61d833a..9467482 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -72,6 +72,8 @@ Optional properties: - wp-gpios: GPIO to which the write-protect pin of the chip is connected. + - address-width : number of address bits (one of 8, 16). + Example: eeprom@52 { -- 2.7.4