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[209.132.180.67]) by mx.google.com with ESMTP id w5-v6si1505818pfn.109.2018.06.26.06.20.34; Tue, 26 Jun 2018 06:20:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b="algw/UwA"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935627AbeFZNSh (ORCPT + 99 others); Tue, 26 Jun 2018 09:18:37 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:50623 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935501AbeFZNPw (ORCPT ); Tue, 26 Jun 2018 09:15:52 -0400 Received: by mail-wm0-f68.google.com with SMTP id e16-v6so1892172wmd.0 for ; Tue, 26 Jun 2018 06:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VCj9H90+ovXjReBaVfSQH5CvcvzciBxLHdjd+ndYlao=; b=algw/UwANNBO1mP8NOPjPQ7LzR9BXgfrF6JZbe2j23CRiaeC4quc9v2Pm9S+28nZQW Uf1RnrtevSQnDWdy3oME8nUVpfliRZHbflCk1KaJOPBh+s59TQ2rXTVjSXQKYX4xc3rz YZzGV2bP1kDQhyhl4DJjYrVYQ1FAGxZDG+k4fMLnl24PHJYajW8B2l5xnkDzRQ4LmvXb SxsYH1O+NiL3nOvOh1DGsY63j5ex5TO/l1Kr8InZzfDWLgr+XcjnYAvWwyI3RsWLJnyQ E6VXTSe7AJsh27qa/Mziek9jIq97/MtUKUwmCtGqACW66dqg0VgJNVLs6UEfJ3/a0j6H tepg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VCj9H90+ovXjReBaVfSQH5CvcvzciBxLHdjd+ndYlao=; b=Xu0+L9fCNeKAUa+aeapjHJSbmgLo9k0txYJIT7uwstelLiqS2Z/ZMJ/xJp7aoXSFaX DDwGaEdQrnj8rzHylH3m8VC5OrtO4jeAmTKM1jn6HpP+Jjzh0ae5kCtAe1kh8wUkehSL wfHlBuzfk1f6ZhSwxQ+382pPXco6ucQ4ttN9EaaVUMGOLTRx1Vn3BPkSo8d0+ucXgJ4a hLi78wxHxyl+skJezu4RtavlxiOx0Da8E41L3GX6Aadi0IETn2vMw+P8Q48YbHf7NHeY yVmMSzMaR6HuHMr7/tde1xNXLybRqSeIikjSXOzkO/cYZI6yl6ZBJnxCCYJnTsdjTxuD 3Snw== X-Gm-Message-State: APt69E3uN5jGWiRMgqWIfJFZwXCYql+QvO/PNsIWfQpPS6H73J3w5dCf IuxgJP1vHsNcpoM8mJv/OdM4MQ== X-Received: by 2002:a1c:5c93:: with SMTP id q141-v6mr1611058wmb.77.1530018950315; Tue, 26 Jun 2018 06:15:50 -0700 (PDT) Received: from andreyknvl0.muc.corp.google.com ([2a00:79e0:15:10:84be:a42a:826d:c530]) by smtp.gmail.com with ESMTPSA id w15-v6sm2162639wrn.25.2018.06.26.06.15.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Jun 2018 06:15:48 -0700 (PDT) From: Andrey Konovalov To: Andrey Ryabinin , Alexander Potapenko , Dmitry Vyukov , Catalin Marinas , Will Deacon , Christoph Lameter , Andrew Morton , Mark Rutland , Nick Desaulniers , Marc Zyngier , Dave Martin , Ard Biesheuvel , "Eric W . Biederman" , Ingo Molnar , Paul Lawrence , Geert Uytterhoeven , Arnd Bergmann , "Kirill A . Shutemov" , Greg Kroah-Hartman , Kate Stewart , Mike Rapoport , kasan-dev@googlegroups.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sparse@vger.kernel.org, linux-mm@kvack.org, linux-kbuild@vger.kernel.org Cc: Kostya Serebryany , Evgeniy Stepanov , Lee Smith , Ramana Radhakrishnan , Jacob Bramley , Ruben Ayrapetyan , Jann Horn , Mark Brand , Chintan Pandya , Andrey Konovalov Subject: [PATCH v4 09/17] khwasan, arm64: enable top byte ignore for the kernel Date: Tue, 26 Jun 2018 15:15:19 +0200 Message-Id: <82571a6721547446b789f759f93bf7f3930541be.1530018818.git.andreyknvl@google.com> X-Mailer: git-send-email 2.18.0.rc2.346.g013aa6912e-goog In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org KHWASAN uses the Top Byte Ignore feature of arm64 CPUs to store a pointer tag in the top byte of each pointer. This commit enables the TCR_TBI1 bit, which enables Top Byte Ignore for the kernel, when KHWASAN is used. Signed-off-by: Andrey Konovalov --- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/mm/proc.S | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index fd208eac9f2a..483aceedad76 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -289,6 +289,7 @@ #define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) +#define TCR_TBI1 (UL(1) << 38) #define TCR_HA (UL(1) << 39) #define TCR_HD (UL(1) << 40) #define TCR_NFD1 (UL(1) << 54) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 03646e6a2ef4..c5175e098d02 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -47,6 +47,12 @@ /* PTWs cacheable, inner/outer WBWA */ #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA +#ifdef CONFIG_KASAN_HW +#define TCR_KASAN_FLAGS TCR_TBI1 +#else +#define TCR_KASAN_FLAGS 0 +#endif + #define MAIR(attr, mt) ((attr) << ((mt) * 8)) /* @@ -440,7 +446,7 @@ ENTRY(__cpu_setup) */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ - TCR_TBI0 | TCR_A1 + TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS tcr_set_idmap_t0sz x10, x9 /* -- 2.18.0.rc2.346.g013aa6912e-goog