Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp5958427imm; Tue, 26 Jun 2018 23:02:47 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIYeprR3b0vW3hQu8z9KWIWdphsLV+u7qdpfhpHEdX1+mHo971xel6BSlN23apn95zJrRQu X-Received: by 2002:a65:65ca:: with SMTP id y10-v6mr3949645pgv.359.1530079367193; Tue, 26 Jun 2018 23:02:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530079367; cv=none; d=google.com; s=arc-20160816; b=Sbwhth5k8NKNGj4L94V4ZA0xtKDQuXEcbJ5Ys+UjjFR41RESL3Go0oAxGmD2sR54YY J0ZtAjXXtyAV3wnCP6X23IhyCLpAwbnoJYa9arTNGZnVv8vd9p/i2Tl7/gWoYKnBo1d6 vSRkH0kURxVzpFsOwFDdyZ3tYqduhkXeitAMMGuTYPZymGd7NiWMFjSmc0v+GmzFLU/r TxUlAZ8svYowxcGlDmqEnmzVkViYIu96HVJG0ZxC616vdv8TFAzHGsOrRSfa20kvwDcD o9nBPO75Iz368NEBn0A1v07pHWuWAkvPHFTx6JuEW5sCkGdxAH7iWh/Uu9l3mLMV4XPV uplg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=gJx3JBjAvTwkd4ZV1aY4gC3RHy5zwT0lF3SSMAarqBc=; b=BGeVVfJq8MqjYyuA74aJEnVfR+tLmTa9blY/vlvEAMz5TdPEoVxSROlAO39sesIKxr 8A+2cVv0gLSxAO9XdqOLcIxmDHRlywK8fAa0dnS1dZYdC8oPlwj6A1TT9TgvO7h4WY09 +XVhj5WKTR/1kZazyM+efjxjpBzqLuw5qosnFoWkUxAhlE8XRiLvt+sKIsnMC2HCbk2q XX2yfO6T+qF8SJ5/4ze8FtgLIb6k/XrASOwx16lDOopLKMj+nJYPXe24FR/iKN5jw7lx QG/InRKVMJQnih4/T3J00cHtLQpGHhRWzH7q/4COgkkCmY5Iv03I+BIDXodYjiHUhpbe J1+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r85-v6si3174674pfa.259.2018.06.26.23.02.32; Tue, 26 Jun 2018 23:02:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753212AbeF0Fq6 (ORCPT + 99 others); Wed, 27 Jun 2018 01:46:58 -0400 Received: from mga02.intel.com ([134.134.136.20]:36289 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750986AbeF0Fq4 (ORCPT ); Wed, 27 Jun 2018 01:46:56 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2018 22:46:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,277,1526367600"; d="scan'208";a="211496373" Received: from shawn-bm6650-bm6350.itwn.intel.com ([10.5.253.27]) by orsmga004.jf.intel.com with ESMTP; 26 Jun 2018 22:46:52 -0700 From: alanx.chiang@intel.com To: linux-i2c@vger.kernel.org Cc: andy.yeh@intel.com, sakari.ailus@linux.intel.com, andriy.shevchenko@linux.intel.com, andriy.shevchenko@intel.com, rajmohan.mani@intel.com, andy.shevchenko@gmail.com, tfiga@chromium.org, jcliang@chromium.org, brgl@bgdev.pl, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alan Chiang Subject: [PATCH v3 1/2] dt-bindings: at24: Add address-width property Date: Wed, 27 Jun 2018 13:46:24 +0800 Message-Id: <1530078385-1546-2-git-send-email-alanx.chiang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530078385-1546-1-git-send-email-alanx.chiang@intel.com> References: <1530078385-1546-1-git-send-email-alanx.chiang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alan Chiang The AT24 series chips use 8-bit address by default. If some chips would like to support more than 8 bits, the at24 driver should be added the compatible field for specfic chips. Provide a flexible way to determine the addressing bits through address-width in this patch. Signed-off-by: Alan Chiang Signed-off-by: Andy Yeh --- since v1: -- Remove the address-width field in the example. since v2: -- Remove redundant space. --- Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index 61d833a..aededdb 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -72,6 +72,8 @@ Optional properties: - wp-gpios: GPIO to which the write-protect pin of the chip is connected. + - address-width: number of address bits (one of 8, 16). + Example: eeprom@52 { -- 2.7.4