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[209.132.180.67]) by mx.google.com with ESMTP id d5-v6si3298337plr.13.2018.06.27.00.05.16; Wed, 27 Jun 2018 00:05:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752642AbeF0HEc (ORCPT + 99 others); Wed, 27 Jun 2018 03:04:32 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:34204 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752106AbeF0HEb (ORCPT ); Wed, 27 Jun 2018 03:04:31 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w5R6wwIl007792; Wed, 27 Jun 2018 09:03:53 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2jv4ycg8jr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 27 Jun 2018 09:03:53 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 889843A; Wed, 27 Jun 2018 07:03:51 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 68FAC13CF; Wed, 27 Jun 2018 07:03:51 +0000 (GMT) Received: from [10.201.21.58] (10.75.127.50) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 27 Jun 2018 09:03:50 +0200 Subject: Re: [PATCH V5 0/5] add iwdg2 support for stm32mp157c To: Ludovic Barre , Wim Van Sebroeck , Guenter Roeck , Rob Herring CC: Maxime Coquelin , , , , References: <1529941383-8653-1-git-send-email-ludovic.Barre@st.com> From: Alexandre Torgue Message-ID: Date: Wed, 27 Jun 2018 09:03:31 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1529941383-8653-1-git-send-email-ludovic.Barre@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG7NODE2.st.com (10.75.127.20) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-06-27_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Guenter On 06/25/2018 05:42 PM, Ludovic Barre wrote: > From: Ludovic Barre > > This patch series updates stm32_iwdg driver to manage pclk > clock by compatible. stm32mp1 requires a pclk clock. > > v5: > -update stm32f429.dtsi > > v4: > -dt-bindings: split and review > > v3: > -remove stm32_iwdg_config structure, just assign the > boolean directly to .dat > > Ludovic Barre (5): > dt-bindings: watchdog: add stm32mp1 support > watchdog: stm32: add pclk feature for stm32mp1 > ARM: dts: stm32: add iwdg2 support for stm32mp157c > ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1 > ARM: dts: stm32: update iwdg with lsi clock name for stm32f429 I will take DT patches in my tree. Thanks alex > > .../devicetree/bindings/watchdog/st,stm32-iwdg.txt | 13 ++- > arch/arm/boot/dts/stm32f429.dtsi | 1 + > arch/arm/boot/dts/stm32mp157c-ed1.dts | 5 + > arch/arm/boot/dts/stm32mp157c.dtsi | 8 ++ > drivers/watchdog/stm32_iwdg.c | 116 +++++++++++++-------- > 5 files changed, 98 insertions(+), 45 deletions(-) >