Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp6292406imm; Wed, 27 Jun 2018 05:32:45 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI6iWFalrJ80Vy8DlR8IGtMh3zPm4Fzh/it1SGIxZZRaaZBmQFO81jdIRe2dQWwUELwtTyy X-Received: by 2002:a65:4ec3:: with SMTP id w3-v6mr5031074pgq.256.1530102765546; Wed, 27 Jun 2018 05:32:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530102765; cv=none; d=google.com; s=arc-20160816; b=u9CB7dP2441m0AwYoMefOCsHsuxkcjv0LLvHXMhpa/fLVOgprl68xpssdj3cVmjcDD vJQ/ygGhzrn+f8UFVTy6glzgmupg3FHbW13UtDYYeR3qEAmd8IbWTQu9JefIr81QTsaz K82U2/3fG/a5EZoUeTV0NbiLLJ4luqQ+uQgH+iWCi2/LESKsIypq4QOBOAdg8OwHluu8 /smzIzyAoeLNW01nowa6ez2jEPR2FJ8/jXnaiyA12mfmhUS0uozk7WlRNlCdH/LFyOGD 0leCF8WWlUGLjIm8fYugWHvwhmRQeyPp8XbLOuYV7ToGC6qnztB7eevpTC1u7OOdKGZn u5og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=L4jvUt63on8EXQ2kZtuc26btLnDYgO6SArZQDpq1qHA=; b=MLpZsLH1O/SuRsBH/eHqkkqbkXKjO3+n+RzfE3TnEmYA2EkiUg2Gi0hHgu/gFS0meT tvalGWPVJXl8V+8NfuDKiUTl1G/a0yYAHihQRliFlJ0RO9Nw5mH90GUOpJe89R34+bBG 84/m1NEwEGLB0bHN0JSrwFV7XvIFr5KqDXx+s13m/BYyia8yS5stCLFI0WvhL7OBdiB9 2WdQVav5H7JlCzAVZKZJKmOy270IEkuZ9aVaVuhUJPoBe6KjpaPv43p7xQTmVYjwH4FK iAGrAlXo8CEOHFzEo3rFntYb3OPAcjiB1C2heV6+W7ECmgH3TlWeKhNoSg+S8qBBW17X YEQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c18-v6si3283823pgp.467.2018.06.27.05.32.30; Wed, 27 Jun 2018 05:32:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933895AbeF0LQq (ORCPT + 99 others); Wed, 27 Jun 2018 07:16:46 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:46138 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S933275AbeF0LQn (ORCPT ); Wed, 27 Jun 2018 07:16:43 -0400 X-UUID: 9d579a0245e5450c8175690966d3232c-20180627 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1220305756; Wed, 27 Jun 2018 19:16:39 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 27 Jun 2018 19:16:39 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 27 Jun 2018 19:16:38 +0800 From: Houlong Wei To: Jassi Brar , Matthias Brugger , Rob Herring CC: Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , Philipp Zabel , Nicolas Boichat , CK HU , Bibby Hsieh , YT Shen , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Monica Wang , Houlong Wei , HS Liao , , Subject: [PATCH v22 1/4] dt-bindings: soc: Add documentation for the MediaTek GCE unit Date: Wed, 27 Jun 2018 19:16:09 +0800 Message-ID: <1530098172-31385-2-git-send-email-houlong.wei@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530098172-31385-1-git-send-email-houlong.wei@mediatek.com> References: <1530098172-31385-1-git-send-email-houlong.wei@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds documentation for the MediaTek Global Command Engine (GCE) unit found in MT8173 SoCs. Signed-off-by: Houlong Wei Signed-off-by: HS Liao --- Hi Rob, I don't add your ACK in this version since the dt-binding description has been changed. Thanks. --- .../devicetree/bindings/mailbox/mtk-gce.txt | 65 ++++++++++++++++++++ include/dt-bindings/gce/mt8173-gce.h | 48 +++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mtk-gce.txt create mode 100644 include/dt-bindings/gce/mt8173-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt new file mode 100644 index 0000000..26f65a4 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -0,0 +1,65 @@ +MediaTek GCE +=============== + +The Global Command Engine (GCE) is used to help read/write registers with +critical time limitation, such as updating display configuration during the +vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. + +CMDQ driver uses mailbox framework for communication. Please refer to +mailbox.txt for generic information about mailbox device-tree bindings. + +Required properties: +- compatible: Must be "mediatek,mt8173-gce" +- reg: Address range of the GCE unit +- interrupts: The interrupt signal from the GCE block +- clock: Clocks according to the common clock binding +- clock-names: Must be "gce" to stand for GCE clock +- thread-num: Maximum threads count of GCE. +- #mbox-cells: Should be 4. + <&phandle channel timeout priority atomic_exec> + phandle: Label name of a gce node. + channel: Channel of mailbox. Be equal to the thread id of GCE. + timeout: Maximum time of software waiting GCE processing done, in unit + of millisecond. + priority: Priority of GCE thread. + atomic_exec: GCE processing continuous packets of commands in atomic + way. + +Required properties for a client device: +- mboxes: Client use mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. +- gce-subsys: Specify the sub-system id which is corresponding to the register + address. + +Optional properties for a client device: +- gce-event: Specify the event if the client has any. Because the event is + parsed by client, so client can replace 'gce-event' with other meaningful + name. + +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as +thread number, sub-system ids, thread priority, event ids. + +Example: + + gce: gce@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + thread-num = CMDQ_THR_MAX_COUNT; + #mbox-cells = <4>; + }; + +Example for a client device: + + mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys"; + mboxes = <&gce 0 2000 CMDQ_THR_PRIO_LOWEST 1>, + <&gce 1 2000 CMDQ_THR_PRIO_LOWEST 1>; + gce-subsys = ; + mutex-event-eof = ; + + ... + }; diff --git a/include/dt-bindings/gce/mt8173-gce.h b/include/dt-bindings/gce/mt8173-gce.h new file mode 100644 index 0000000..89eb3b8 --- /dev/null +++ b/include/dt-bindings/gce/mt8173-gce.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Houlong Wei + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8173_H +#define _DT_BINDINGS_GCE_MT8173_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +#define CMDQ_THR_MAX_COUNT 16 + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_OVL0_EOF 39 +#define CMDQ_EVENT_DISP_OVL1_EOF 40 +#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 + +#endif -- 1.7.9.5