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Date:   Fri, 29 Jun 2018 22:08:59 +0200 (CEST)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     Fenghua Yu <fenghua.yu@intel.com>
cc:     Dave Hansen <dave.hansen@intel.com>,
        Ingo Molnar <mingo@redhat.com>, H Peter Anvin <hpa@zytor.com>,
        Ashok Raj <ashok.raj@intel.com>,
        Alan Cox <alan@linux.intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Rafael Wysocki <rafael.j.wysocki@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v2 2/4] x86/split_lock: Align x86_capability to unsigned
 long to avoid split locked access
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On Fri, 29 Jun 2018, Fenghua Yu wrote:

> On Fri, Jun 29, 2018 at 06:35:39PM +0200, Thomas Gleixner wrote:
> > On Fri, 29 Jun 2018, Dave Hansen wrote:
> > 
> > Plus what enforces proper alignment for the other capability related
> > u32 arrays? 
> 
> Do you want me to enforce unsigned long alignment for all that are used by
> locked BTS/BTR?

If there are variables which might be unaligned and accessed with locked
instructions and you have them identified, then why are you asking whether
they should be fixed?

Ignoring them because they do not trigger #AC right now, is only the
correct answer if you are a follower of the 'works by chance' cult.

Yeah, I know that most of this industry just works by chance....

> Or you think we can push the patches upstream to allow broad test to find
> and fix the issues?

And all testers have access to the emulator running the design of the
silicon with that new feature which will be released in a year from now?

Aside of that we merge the patches when they are ready and done. And AFAICT
there is enough homework to be finished before that.

Thanks,

	tglx