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[209.132.180.67]) by mx.google.com with ESMTP id r70-v6si8882421pfa.44.2018.07.02.08.46.53; Mon, 02 Jul 2018 08:47:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752607AbeGBPp2 (ORCPT + 99 others); Mon, 2 Jul 2018 11:45:28 -0400 Received: from iolanthe.rowland.org ([192.131.102.54]:38832 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1752216AbeGBPp1 (ORCPT ); Mon, 2 Jul 2018 11:45:27 -0400 Received: (qmail 3168 invoked by uid 2102); 2 Jul 2018 11:45:26 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 2 Jul 2018 11:45:26 -0400 Date: Mon, 2 Jul 2018 11:45:26 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Paul Menzel cc: Greg Kroah-Hartman , , , Subject: Re: [PATCH] usb/host/pci-quirks: Only reset USB bus on NVIDIA devices In-Reply-To: <20180701211607.7833-1-pmenzel@molgen.mpg.de> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 1 Jul 2018, Paul Menzel wrote: > Currently, on the AMD board Asus F2A85-M Pro there is a 100 ms delay as > the USB bus of each of the two OHCI PCI devices is reset. As a 50 ms > delay is done per the USB specification. > > Commit c6187597 (OHCI: final fix for NVIDIA problems (I hope)) > unconditionally does the bus reset for > all chipsets, while it was only doen for NVIDIA chipsets before. I don't follow this at all. Prior to that commit, the bus reset (i.e., writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); ) was performed unconditionally for _all_ controllers. (However, the 50-ms delay was used only for NVIDIA hardware.) Following that commit, the reset is performed for all controllers, but only if the HCFS bitfield is nonzero. > As it should not be needed for non-NVIDIA chipsets, only do the reset > for Nvidia devices. Therefore this reasoning is wrong. > Tested on Asus F2A85-M PRO and ASRock E350M1. The USB keyboard works and > the LUKS passphrase can be e > ntered. Unfortunately, there is a wide variety of OHCI controller hardware available. Something that works on one or two controllers might not work on another. Besides, doesn't it seem like a bad idea to reset the controller while leaving devices on the USB bus in whatever state they happened to be? Alan Stern > Signed-off-by: Paul Menzel > Cc: Greg Kroah-Hartman > Cc: linux-usb@vger.kernel.org > Cc: Alan Stern > Cc: linux-kernel@vger.kernel.org > Cc: stable@vger.kernel.org > --- > drivers/usb/host/pci-quirks.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c > index 3625a5c1a41b..f6b1a9bbe301 100644 > --- a/drivers/usb/host/pci-quirks.c > +++ b/drivers/usb/host/pci-quirks.c > @@ -784,7 +784,7 @@ static void quirk_usb_handoff_ohci(struct pci_dev *pdev) > writel((u32) ~0, base + OHCI_INTRDISABLE); > > /* Reset the USB bus, if the controller isn't already in RESET */ > - if (control & OHCI_HCFS) { > + if ((pdev->vendor == PCI_VENDOR_ID_NVIDIA) && (control & OHCI_HCFS)) { > /* Go into RESET, preserving RWC (and possibly IR) */ > writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); > readl(base + OHCI_CONTROL); >