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Date:   Mon, 2 Jul 2018 22:01:31 -0400 (EDT)
From:   Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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Subject: Re: [RFC PATCH for 4.18] rseq: use __u64 for rseq_cs fields,
 validate user inputs
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Thread-Topic: rseq: use __u64 for rseq_cs fields, validate user inputs
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----- On Jul 2, 2018, at 9:19 PM, Mathieu Desnoyers mathieu.desnoyers@effic=
ios.com wrote:

> ----- On Jul 2, 2018, at 7:37 PM, Andy Lutomirski luto@amacapital.net wro=
te:
>=20
>>> On Jul 2, 2018, at 4:22 PM, Mathieu Desnoyers <mathieu.desnoyers@effici=
os.com>
>>> wrote:
>>>=20
>>> ----- On Jul 2, 2018, at 7:16 PM, Mathieu Desnoyers
>>> mathieu.desnoyers@efficios.com wrote:
>>>=20
>>>> ----- On Jul 2, 2018, at 7:06 PM, Linus Torvalds torvalds@linux-founda=
tion.org
>>>> wrote:
>>>>=20
>>>>> On Mon, Jul 2, 2018 at 4:00 PM Mathieu Desnoyers
>>>>> <mathieu.desnoyers@efficios.com> wrote:
>>>>>>=20
>>>>>> Unfortunately, that rseq->rseq_cs field needs to be updated by user-=
space
>>>>>> with single-copy atomicity. Therefore, we want 32-bit user-space to =
initialize
>>>>>> the padding with 0, and only update the low bits with single-copy at=
omicity.
>>>>>=20
>>>>> Well... It's actually still single-copy atomicity as a 64-bit value.
>>>>>=20
>>>>> Why? Because it doesn't matter how you write the upper bits. You'll b=
e
>>>>> writing the same value to them (zero) anyway.
>>>>>=20
>>>>> So who cares if the write ends up being two instructions, because the
>>>>> write to the upper bits doesn't actually *do* anything.
>>>>>=20
>>>>> Hmm?
>>>>=20
>>>> Are there any kind of guarantees that a __u64 update on a 32-bit archi=
tecture
>>>> won't be torn into something daft like byte-per-byte stores when perfo=
rmed
>>>> from C code ?
>>>>=20
>>>> I don't worry whether the upper bits get updated or how, but I really =
care
>>>> about not having store tearing of the low bits update.
>>>=20
>>> For the records, most updates of those low bits are done in assembly
>>> from critical sections, for which we control exactly how the update is
>>> performed.
>>>=20
>>> However, there is one helper function in user-space that updates that v=
alue
>>> from C through a volatile store, e.g.:
>>>=20
>>> static inline void rseq_prepare_unload(void)
>>> {
>>>        __rseq_abi.rseq_cs =3D 0;
>>> }
>>=20
>> How about making the field be:
>>=20
>> union {
>> __u64 rseq_cs;
>> struct {
>>   __u32 rseq_cs_low;
>>   __u32 rseq_cs_high;
>> };
>> };
>>=20
>> 32-bit user code that cares about performance can just write to rseq_cs_=
low
>> because it already knows that rseq_cs_high =3D=3D 0.
>>=20
>> The header could even supply a static inline helper write_rseq_cs() that
>> atomically writes a pointer and just does the right thing for 64-bit, fo=
r
>> 32-bit BE, and for 32-bit LE.
>>=20
>> I think the union really is needed because we can=E2=80=99t rely on user=
 code being
>> built with -fno-strict-aliasing.  Or the helper could use inline asm.
>>=20
>> Anyway, the point is that we get optimal code generation (a single instr=
uction
>> write of the correct number of bits) without any compat magic in the ker=
nel.
>=20
> That works for me! Any objection from anyone else for this approach ?

One thing to consider is how we will implement the load of that pointer
on the kernel side. Strictly-speaking, the rseq uapi talks about single-cop=
y
atomicity, and does not specify _which_ thread is expected to update that
pointer. So arguably, the common case is that the current thread is updatin=
g
it, which would allow the kernel to read it piece-wise. However, nothing
prevents user-space from updating it from another thread with single-copy
atomicity.

So in order to be on the safe side, I prefer to guarantee single-copy
atomicity of the get_user() load from the kernel that reads this pointer.
This means a 32-bit kernel would have to perform two independent loads:
one for low bits, one for high bits.

So it does look like we need some __LP64__ ifdefery even with the union
trick. Therefore, I'm not convinced the union is useful at all.

Thoughts ?

Thanks,

Mathieu

--=20
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com