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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 3 Jul 2018 09:55:49 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w638tmPg41222396 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 3 Jul 2018 08:55:48 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B5D6952057; Tue, 3 Jul 2018 11:56:13 +0100 (BST) Received: from osiris (unknown [9.152.212.90]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTPS id 0B8D752050; Tue, 3 Jul 2018 11:56:13 +0100 (BST) Date: Tue, 3 Jul 2018 10:55:46 +0200 From: Heiko Carstens To: Peter Zijlstra Cc: Mathieu Desnoyers , Linus Torvalds , Andy Lutomirski , Thomas Gleixner , linux-kernel , linux-api , "Paul E. McKenney" , Boqun Feng , Dave Watson , Paul Turner , Andrew Morton , Russell King , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Chris Lameter , Ben Maurer , rostedt , Josh Triplett , Catalin Marinas , Will Deacon , Michael Kerrisk , Joel Fernandes , michal.simek@xilinx.com, Martin Schwidefsky , Vasily Gorbik Subject: Re: [RFC PATCH for 4.18] rseq: use __u64 for rseq_cs fields, validate user inputs References: <825871008.10839.1530573419561.JavaMail.zimbra@efficios.com> <1959930320.10843.1530573742647.JavaMail.zimbra@efficios.com> <8B2E4CEB-3080-4602-8B62-774E400892EB@amacapital.net> <459661281.10865.1530580742205.JavaMail.zimbra@efficios.com> <858886246.10882.1530583291379.JavaMail.zimbra@efficios.com> <1776351430.10902.1530585009519.JavaMail.zimbra@efficios.com> <20180703081449.GT2494@hirez.programming.kicks-ass.net> <20180703082955.GH3704@osiris> <20180703084312.GU2494@hirez.programming.kicks-ass.net> MIME-Version: 1.0 In-Reply-To: <20180703084312.GU2494@hirez.programming.kicks-ass.net> X-TM-AS-GCONF: 00 x-cbid: 18070308-0016-0000-0000-000001E2CF8B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18070308-0017-0000-0000-000032372C0D Message-Id: <20180703085546.GJ3704@osiris> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-07-03_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=347 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807030101 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > > We're piece-wise enabling rseq across architectures anyway, and when the > > > relevant maintains do this, they can have a look at their > > > {get,put}_user() implementations and fix them. > > > > > > If you rely on get_user(u64) working, that means microblaze is already > > > broken, but I suppose it already was, since their rseq enablement patch > > > is extremely dodgy. Michal? > > > > s390 uses the mvcos instruction to implement get_user(). That instruction > > is not defined to be atomic, but may copy bytes piecemeal.. I had the > > impression that the rseq fields are supposed to be updated within the > > context of a single thread (user + kernel space). > > > > However if another user space thread is allowed to do this as well, then > > the get_user() approach won't fly on s390. > > > > That leaves the question: does it even make sense for a thread to update > > the rseq structure of a different thread? > > The problem is interrupts; we need interrupts on the CPU doing the store > to observe either the old or the new value, not a mix. > > If mvcos does not guarantee that, we're having problems. Is there a > reason get_user() cannot use a 'regular' load? Well, that's single instruction semantics. This is something we actually can guarantee, since the mvcos instruction itself won't be interrupted and copies all 1/2/4/8 bytes in a row. So we are talking about that single instructions are required and not atomic accesses?