Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp1098909imm; Tue, 3 Jul 2018 05:36:38 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJZzKzlnutKMTXDSc85nK5SnaXN2FnXjUrtE609dIIoUNPaVkYZDcIljgQezq2MSIXMwVTV X-Received: by 2002:a17:902:8a4:: with SMTP id 33-v6mr29539098pll.343.1530621398769; Tue, 03 Jul 2018 05:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530621398; cv=none; d=google.com; s=arc-20160816; b=pSprk9xRDjJJH2OTEEbmyZwkKOLhxzNrn+8NaG9tCydVQToJhQuMyT2VM+27OjPaQb PoaYV+dkhWOBnt52H9DMDLEiKrup6UYGAmUk2RNxmDIB+OtCADbFQVWxigvf2xrncJhf F6Sr4xhMD942Luj4vRVyEbwOugtvaJuIduf7k0Nr02P4ZmQCfj/vzN1GIR0fymT2Hd8X z4YVzihXQCYewtbbKk3Osxviiy0gSIRe92ddmI90C16B0DtT4tuS2ubrcnYuFbMKLNol QaSIeeqG09fEn43Fm1CaygCNDCf2eLXhQq6CBtKMD1ETaI537UWdhcq3j3cgbvyRiGI2 tt5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=x2w6U476zZP4+jCoJbedcXjYBSa/JX+w8NhUn/Xnrkw=; b=cVNHEvVLE9vN+KAOCo8DcH9J2Mb7DxyagunwtWYLKZCxR1eOFiqMd2pwwpTBU/862c vHJY1KmW4o1LiD4zRyF5TP2NaSdUPyBqZFUCEuan1JG5M0An+Ph2xrF3nF7+XnRrhu97 qTEHfWSWiOP2xieQQyG4v3c5jYUr5dOFJf8RF6+viokzv1/7Cf90Co71pRhy6C50pddd AeNgfz9hbiIVUz1935WY2GUFD7Lt6WfNbusE/YMtpkiDWqXtm6npp+pnKfo6AngiqNwl CFgKMewV3uCg93L+IgLJHq3dSSMiFySXLqgzH0XyLiLnvsD5oN/YtLJdVzKqr+b4/8v9 ORgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=nrvxwJkp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 75-v6si963704pgh.110.2018.07.03.05.36.24; Tue, 03 Jul 2018 05:36:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=nrvxwJkp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753377AbeGCMcf (ORCPT + 99 others); Tue, 3 Jul 2018 08:32:35 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:46646 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752612AbeGCMcd (ORCPT ); Tue, 3 Jul 2018 08:32:33 -0400 From: Paul Cercueil To: Vinod Koul , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , Zubair Lutfullah Kakakhel Cc: Mathieu Malaterre , Daniel Silsby , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Paul Cercueil Subject: [PATCH 03/14] dmaengine: dma-jz4780: Use 4-word descriptors Date: Tue, 3 Jul 2018 14:32:03 +0200 Message-Id: <20180703123214.23090-4-paul@crapouillou.net> In-Reply-To: <20180703123214.23090-1-paul@crapouillou.net> References: <20180703123214.23090-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1530621151; bh=x2w6U476zZP4+jCoJbedcXjYBSa/JX+w8NhUn/Xnrkw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=nrvxwJkpxw+mFiViEuLIYEvOOgjZbOfzTrXJ6uf4tQkbsHOs1mfm/lcTUYYcamlYyrtsEut+EzUG6vIBhMPMwk1d9mpEXPbAnUVUpbJ2rlvpbLuV9hYhZAcj9MGfpffvb6KKBld9K50MbFRxn/0O++T4PgZST7Pg5tDiD7m742Q= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The only information we use in the 8-word version of the hardware DMA descriptor that is not present in the 4-word version is the transfer type, aka. the ID of the source or recipient device. Since the transfer type will never change for a DMA channel in use, we can just set it once for all in the corresponding DMA register before starting any transfer. This has several benefits: * the driver will handle twice as many hardware DMA descriptors; * the driver is closer to support the JZ4740, which only supports 4-word hardware DMA descriptors; * the JZ4770 SoC needs the transfer type to be set in the corresponding DMA register anyway, even if 8-word descriptors are in use. Signed-off-by: Paul Cercueil --- drivers/dma/dma-jz4780.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 4d234caf5d62..cd2cd70fd843 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -93,17 +93,12 @@ * @dtc: transfer count (number of blocks of the transfer size specified in DCM * to transfer) in the low 24 bits, offset of the next descriptor from the * descriptor base address in the upper 8 bits. - * @sd: target/source stride difference (in stride transfer mode). - * @drt: request type */ struct jz4780_dma_hwdesc { uint32_t dcm; uint32_t dsa; uint32_t dta; uint32_t dtc; - uint32_t sd; - uint32_t drt; - uint32_t reserved[2]; }; /* Size of allocations for hardware descriptor blocks. */ @@ -280,7 +275,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, desc->dcm = JZ_DMA_DCM_SAI; desc->dsa = addr; desc->dta = config->dst_addr; - desc->drt = jzchan->transfer_type; width = config->dst_addr_width; maxburst = config->dst_maxburst; @@ -288,7 +282,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, desc->dcm = JZ_DMA_DCM_DAI; desc->dsa = config->src_addr; desc->dta = addr; - desc->drt = jzchan->transfer_type; width = config->src_addr_width; maxburst = config->src_maxburst; @@ -433,9 +426,10 @@ static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( tsz = jz4780_dma_transfer_size(dest | src | len, &jzchan->transfer_shift); + jzchan->transfer_type = JZ_DMA_DRT_AUTO; + desc->desc[0].dsa = src; desc->desc[0].dta = dest; - desc->desc[0].drt = JZ_DMA_DRT_AUTO; desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI | tsz << JZ_DMA_DCM_TSZ_SHIFT | JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT | @@ -490,9 +484,12 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) (jzchan->curr_hwdesc + 1) % jzchan->desc->count; } - /* Use 8-word descriptors. */ - jz4780_dma_chn_writel(jzdma, jzchan->id, - JZ_DMA_REG_DCS, JZ_DMA_DCS_DES8); + /* Use 4-word descriptors. */ + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); + + /* Set transfer type. */ + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT, + jzchan->transfer_type); /* Write descriptor address and initiate descriptor fetch. */ desc_phys = jzchan->desc->desc_phys + @@ -502,7 +499,7 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) /* Enable the channel. */ jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, - JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE); + JZ_DMA_DCS_CTE); } static void jz4780_dma_issue_pending(struct dma_chan *chan) -- 2.18.0