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[209.132.180.67]) by mx.google.com with ESMTP id d11-v6si1635238pll.255.2018.07.03.11.53.52; Tue, 03 Jul 2018 11:54:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934537AbeGCSv6 (ORCPT + 99 others); Tue, 3 Jul 2018 14:51:58 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:45192 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934488AbeGCSv4 (ORCPT ); Tue, 3 Jul 2018 14:51:56 -0400 Received: from p4fea482e.dip0.t-ipconnect.de ([79.234.72.46] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1faQOZ-00012g-TB; Tue, 03 Jul 2018 20:51:24 +0200 Date: Tue, 3 Jul 2018 20:51:23 +0200 (CEST) From: Thomas Gleixner To: Jarkko Sakkinen cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, linux-sgx@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , Tom Lendacky , Borislav Petkov , Konrad Rzeszutek Wilk , Greg Kroah-Hartman , Janakarajan Natarajan , David Woodhouse , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" Subject: Re: [PATCH v12 03/13] x86/sgx: add SGX definitions to msr-index.h In-Reply-To: <20180703182118.15024-4-jarkko.sakkinen@linux.intel.com> Message-ID: References: <20180703182118.15024-1-jarkko.sakkinen@linux.intel.com> <20180703182118.15024-4-jarkko.sakkinen@linux.intel.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 3 Jul 2018, Jarkko Sakkinen wrote: x86/msr: Add .... > From: Sean Christopherson > > ENCLS and ENCLU are usable if and only if SGX_ENABLE is set and After > SGX is activated the IA32_SGXLEPUBKEYHASHn MSRs are writable if > SGX_LC_WR is set and the feature control is locked. > > SGX related bits in IA32_FEATURE_CONTROL cannot be set before SGX is > activated by the pre-boot firmware. SGX activation is triggered by > setting bit 0 in the MSR 0x7a. Until SGX is activated, the LE hash MSRs > are writable to allow pre-boot firmware to lock down the LE root key > with a non-Intel value. > > Signed-off-by: Sean Christopherson > Co-developed-by: Haim Cohen Lacks SOB > --- > arch/x86/include/asm/msr-index.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index fda2114197b3..a7355fb7344f 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -479,6 +479,8 @@ > #define FEATURE_CONTROL_LOCKED (1<<0) > #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) > #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) > +#define FEATURE_CONTROL_SGX_ENABLE (1<<18) Tabs not spaces please. checkpatch.pl would have told you > +#define FEATURE_CONTROL_SGX_LE_WR (1<<17) Thanks, tglx